mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-23 05:29:36 +02:00
+ optimized code generation on sparc
+ some stuff for pic code on sparc added
This commit is contained in:
florian
parent
d5d331bced
commit
00324d38bf
compiler
@ -71,8 +71,10 @@ implementation
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procedure tcgloadnode.generate_picvaraccess;
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begin
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{$ifndef sparc}
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location.reference.base:=current_procinfo.got;
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location.reference.symbol:=objectlibrary.newasmsymbol(tglobalvarsym(symtableentry).mangledname+'@GOT',AB_EXTERNAL,AT_DATA);
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{$endif sparc}
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end;
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@ -235,7 +237,8 @@ implementation
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globalsymtable,
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staticsymtable :
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begin
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if cs_create_pic in aktmoduleswitches then
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if (target_info.system=system_powerpc_darwin) and
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(cs_create_pic in aktmoduleswitches) then
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begin
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generate_picvaraccess;
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if not(pi_needs_got in current_procinfo.flags) then
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@ -951,7 +954,11 @@ begin
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end.
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{
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$Log$
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Revision 1.135 2005-01-04 16:37:09 peter
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Revision 1.136 2005-01-23 17:14:21 florian
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+ optimized code generation on sparc
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+ some stuff for pic code on sparc added
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Revision 1.135 2005/01/04 16:37:09 peter
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* don't release temps for array of ansistring
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Revision 1.134 2004/12/18 15:48:27 florian
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@ -354,6 +354,10 @@ implementation
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{$ifdef SUPPORT_MMX}
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registersmmx:=0;
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{$endif SUPPORT_MMX}
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if (cs_create_pic in aktmoduleswitches) and
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not(symtableentry.typ in [paravarsym,localvarsym]) then
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include(current_procinfo.flags,pi_needs_got);
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case symtableentry.typ of
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absolutevarsym :
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;
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@ -1177,7 +1181,11 @@ begin
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end.
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{
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$Log$
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Revision 1.142 2004-12-26 16:21:39 peter
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Revision 1.143 2005-01-23 17:14:21 florian
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+ optimized code generation on sparc
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+ some stuff for pic code on sparc added
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Revision 1.142 2004/12/26 16:21:39 peter
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* resourcestring does not need exception frame
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Revision 1.141 2004/12/07 13:52:54 michael
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@ -121,13 +121,10 @@ implementation
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uses
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globals,verbose,systems,cutils,
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symdef,paramgr,
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tgobj,procinfo,cpupi;
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tgobj,
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procinfo,cpupi;
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{****************************************************************************
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This is private property, keep out! :)
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****************************************************************************}
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function TCgSparc.IsSimpleRef(const ref:treference):boolean;
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begin
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if (ref.base=NR_NO) and (ref.index<>NR_NO) then
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@ -153,6 +150,31 @@ implementation
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ref.base:=ref.index;
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ref.index:=NR_NO;
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end;
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if (cs_create_pic in aktmoduleswitches) and
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assigned(ref.symbol) then
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begin
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tmpreg:=GetIntRegister(list,OS_INT);
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reference_reset(tmpref);
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tmpref.symbol:=ref.symbol;
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tmpref.refaddr:=addr_pic;
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if not(pi_needs_got in current_procinfo.flags) then
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internalerror(200501161);
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tmpref.index:=current_procinfo.got;
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list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
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ref.symbol:=nil;
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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else
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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ref.base:=tmpreg;
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end;
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end;
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{ When need to use SETHI, do it first }
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if assigned(ref.symbol) or
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(ref.offset<simm13lo) or
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@ -164,28 +186,31 @@ implementation
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tmpref.offset:=ref.offset;
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tmpref.refaddr:=addr_hi;
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list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,tmpreg));
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{ Load the low part is left }
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{$warning TODO Maybe not needed to load symbol}
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tmpref.refaddr:=addr_lo;
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list.concat(taicpu.op_reg_ref_reg(A_OR,tmpreg,tmpref,tmpreg));
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{ The offset and symbol are loaded, reset in reference }
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ref.offset:=0;
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ref.symbol:=nil;
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{ Only an index register or offset is allowed }
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if tmpreg<>NR_NO then
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if (ref.offset=0) and (ref.index=NR_NO) and
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(ref.base=NR_NO) then
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begin
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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ref.refaddr:=addr_lo;
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end
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else
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begin
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{ Load the low part is left }
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tmpref.refaddr:=addr_lo;
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list.concat(taicpu.op_reg_ref_reg(A_OR,tmpreg,tmpref,tmpreg));
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ref.offset:=0;
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{ symbol is loaded }
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ref.symbol:=nil;
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end;
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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else
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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ref.base:=tmpreg;
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end;
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ref.base:=tmpreg;
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end;
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end;
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if (ref.base<>NR_NO) then
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@ -236,10 +261,22 @@ implementation
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procedure Tcgsparc.init_register_allocators;
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begin
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inherited init_register_allocators;
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7],
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first_int_imreg,[]);
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if (cs_create_pic in aktmoduleswitches) and
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(pi_needs_got in current_procinfo.flags) then
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begin
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current_procinfo.got:=NR_L7;
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6],
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first_int_imreg,[]);
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end
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else
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7],
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first_int_imreg,[]);
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBFS,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
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RS_F8,RS_F9,RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15,
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@ -540,34 +577,62 @@ implementation
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procedure TCgSparc.a_loadaddr_ref_reg(list : TAasmOutput;const ref : TReference;r : tregister);
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var
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tmpref : treference;
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hreg : tregister;
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tmpref,href : treference;
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hreg,tmpreg : tregister;
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begin
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if (ref.base=NR_NO) and (ref.index<>NR_NO) then
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href:=ref;
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if (href.base=NR_NO) and (href.index<>NR_NO) then
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internalerror(200306171);
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if (cs_create_pic in aktmoduleswitches) and
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assigned(href.symbol) then
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begin
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tmpreg:=GetIntRegister(list,OS_ADDR);
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reference_reset(tmpref);
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tmpref.symbol:=href.symbol;
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tmpref.refaddr:=addr_pic;
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if not(pi_needs_got in current_procinfo.flags) then
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internalerror(200501161);
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tmpref.base:=current_procinfo.got;
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list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
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href.symbol:=nil;
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if (href.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,href.index,tmpreg));
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href.index:=tmpreg;
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end
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else
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begin
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if href.base<>NR_NO then
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href.index:=tmpreg
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else
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href.base:=tmpreg;
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end;
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end;
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{ At least big offset (need SETHI), maybe base and maybe index }
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if assigned(ref.symbol) or
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(ref.offset<simm13lo) or
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(ref.offset>simm13hi) then
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if assigned(href.symbol) or
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(href.offset<simm13lo) or
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(href.offset>simm13hi) then
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begin
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hreg:=GetAddressRegister(list);
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reference_reset(tmpref);
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tmpref.symbol := ref.symbol;
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tmpref.offset := ref.offset;
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tmpref.symbol := href.symbol;
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tmpref.offset := href.offset;
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tmpref.refaddr := addr_hi;
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list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,hreg));
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{ Only the low part is left }
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tmpref.refaddr:=addr_lo;
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list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,tmpref,hreg));
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if ref.base<>NR_NO then
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if href.base<>NR_NO then
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begin
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if ref.index<>NR_NO then
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if href.index<>NR_NO then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.base,hreg));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,r));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,hreg));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
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end
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else
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.base,r));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,r));
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end
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else
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begin
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@ -577,33 +642,33 @@ implementation
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end
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else
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{ At least small offset, maybe base and maybe index }
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if ref.offset<>0 then
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if href.offset<>0 then
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begin
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if ref.base<>NR_NO then
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if href.base<>NR_NO then
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begin
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if ref.index<>NR_NO then
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if href.index<>NR_NO then
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begin
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hreg:=GetAddressRegister(list);
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list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,hreg));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,r));
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list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,hreg));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
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end
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else
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list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,r));
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list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,r));
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end
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else
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list.concat(taicpu.op_const_reg(A_MOV,ref.offset,r));
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list.concat(taicpu.op_const_reg(A_MOV,href.offset,r));
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end
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else
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{ Both base and index }
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if ref.index<>NR_NO then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,r))
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if href.index<>NR_NO then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,href.base,href.index,r))
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else
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{ Only base }
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if ref.base<>NR_NO then
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a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref.base,r)
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if href.base<>NR_NO then
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a_load_reg_reg(list,OS_ADDR,OS_ADDR,href.base,r)
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else
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{ only offset, can be generated by absolute }
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a_load_const_reg(list,OS_ADDR,ref.offset,r);
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a_load_const_reg(list,OS_ADDR,href.offset,r);
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end;
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@ -650,7 +715,7 @@ implementation
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if (a=0) then
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list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],reg,NR_G0,reg))
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else
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a_op_const_reg_reg(list,op,size,a,reg,reg);
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handle_reg_const_reg(list,TOpCG2AsmOp[op],reg,a,reg);
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end;
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@ -689,9 +754,8 @@ implementation
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begin
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if ispowerof2(a,power) then
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begin
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{ we can't do this easily in the asm. optimizer; overflow checking code
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might depend on a set Y }
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a_op_const_reg_reg(list,OP_SHL,size,power,src,dst);
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{ can be done with a shift }
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inherited a_op_const_reg_reg(list,op,size,a,src,dst);
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exit;
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end;
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end;
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@ -942,6 +1006,11 @@ implementation
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end
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else
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list.concat(Taicpu.Op_reg_const_reg(A_SAVE,NR_STACK_POINTER_REG,-LocalSize,NR_STACK_POINTER_REG));
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if (cs_create_pic in aktmoduleswitches) and
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(pi_needs_got in current_procinfo.flags) then
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begin
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current_procinfo.got:=NR_L7;
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end;
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end;
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@ -1341,7 +1410,11 @@ begin
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end.
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{
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$Log$
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Revision 1.101 2005-01-07 16:22:54 florian
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Revision 1.102 2005-01-23 17:14:21 florian
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+ optimized code generation on sparc
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+ some stuff for pic code on sparc added
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Revision 1.101 2005/01/07 16:22:54 florian
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+ implemented abi compliant handling of strucutured functions results on sparc platform
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Revision 1.100 2005/01/01 13:19:09 florian
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@ -56,16 +56,19 @@ implementation
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else if offset<0 then
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GetReferenceString:=GetReferenceString+ToStr(offset);
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case refaddr of
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addr_hi :
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addr_hi:
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GetReferenceString:='%hi('+GetReferenceString+')';
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addr_lo :
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addr_lo:
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GetReferenceString:='%lo('+GetReferenceString+')';
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end;
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end
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else
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begin
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if assigned(symbol) then
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{$ifdef extdebug}
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if assigned(symbol) and
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not(refaddr in [addr_pic,addr_lo]) then
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internalerror(2003052601);
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{$endif extdebug}
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if base<>NR_NO then
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GetReferenceString:=GetReferenceString+gas_regname(base);
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if index=NR_NO then
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@ -76,11 +79,24 @@ implementation
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GetReferenceString:=GetReferenceString+'+'+ToStr(offset)
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else if offset<0 then
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GetReferenceString:=GetReferenceString+ToStr(offset);
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{
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else if (offset=0) and not(assigned(symbol)) then
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GetReferenceString:=GetReferenceString+ToStr(offset);
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}
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if assigned(symbol) then
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begin
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if refaddr=addr_lo then
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GetReferenceString:='%lo('+symbol.name+')+'+GetReferenceString
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else
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GetReferenceString:=symbol.name+'+'+GetReferenceString;
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end;
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end
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else
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begin
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if Offset<>0 then
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{$ifdef extdebug}
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if (Offset<>0) or assigned(symbol) then
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internalerror(2003052603);
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{$endif extdebug}
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GetReferenceString:=GetReferenceString+'+'+gas_regname(index);
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end;
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end;
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@ -97,7 +113,8 @@ implementation
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top_const:
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getopstr:=tostr(longint(val));
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top_ref:
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if Oper.ref^.refaddr=addr_no then
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if (oper.ref^.refaddr in [addr_no,addr_pic]) or ((oper.ref^.refaddr=addr_lo) and ((oper.ref^.base<>NR_NO) or
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(oper.ref^.index<>NR_NO))) then
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getopstr:='['+getreferencestring(ref^)+']'
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else
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getopstr:=getreferencestring(ref^);
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@ -189,7 +206,11 @@ begin
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end.
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{
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$Log$
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Revision 1.30 2004-10-31 21:45:04 peter
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Revision 1.31 2005-01-23 17:14:21 florian
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+ optimized code generation on sparc
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+ some stuff for pic code on sparc added
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Revision 1.30 2004/10/31 21:45:04 peter
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* generic tlocation
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* move tlocation to cgutils
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