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Added FPv4_d16 FPU instructions, and a few extra registers

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git-svn-id: branches/laksen/arm-embedded@22596 -
This commit is contained in:
Jeppe Johansen 2012-10-08 20:04:14 +00:00
parent 3e963a49e2
commit 0087661fb5
20 changed files with 143 additions and 15 deletions
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31
compiler/arm/armatt.inc
View File

@ -296,6 +296,35 @@
'itttt',
'tbb',
'tbh',
'movw',
'cbz',
'cbnz'
'cbnz',
'vabs',
'vadd',
'vcmp',
'vcmpe',
'vcvt',
'vdiv',
'vldm',
'vldr',
'vmov',
'vmrs',
'vmsr',
'vmul',
'vmla',
'vmls',
'vnmla',
'vnmls',
'vfma',
'vfms',
'vfnma',
'vfnms',
'vneg',
'vnmul',
'vpop',
'vpush',
'vsqrt',
'vstm',
'vstr',
'vsub'
);

29
compiler/arm/armatts.inc
View File

@ -297,5 +297,34 @@ attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE
);

34
compiler/arm/armins.dat
View File

@ -753,5 +753,37 @@ reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7
[TBB]
[TBH]
[MOVW]
[CBZ]
[CBNZ]
[CBNZ]
; FPv4-s16 - ARMv7M floating point
[VABS]
[VADD]
[VCMP]
[VCMPE]
[VCVT]
[VDIV]
[VLDM]
[VLDR]
[VMOV]
[VMRS]
[VMSR]
[VMUL]
[VMLA]
[VMLS]
[VNMLA]
[VNMLS]
[VFMA]
[VFMS]
[VFNMA]
[VFNMS]
[VNEG]
[VNMUL]
[VPOP]
[VPUSH]
[VSQRT]
[VSTM]
[VSTR]
[VSUB]

31
compiler/arm/armop.inc
View File

@ -296,6 +296,35 @@ A_ITETT,
A_ITTTT,
A_TBB,
A_TBH,
A_MOVW,
A_CBZ,
A_CBNZ
A_CBNZ,
A_VABS,
A_VADD,
A_VCMP,
A_VCMPE,
A_VCVT,
A_VDIV,
A_VLDM,
A_VLDR,
A_VMOV,
A_VMRS,
A_VMSR,
A_VMUL,
A_VMLA,
A_VMLS,
A_VNMLA,
A_VNMLS,
A_VFMA,
A_VFMS,
A_VFNMA,
A_VFNMS,
A_VNEG,
A_VNMUL,
A_VPOP,
A_VPUSH,
A_VSQRT,
A_VSTM,
A_VSTR,
A_VSUB
);

3
compiler/arm/armreg.dat
View File

@ -109,4 +109,5 @@ D31,$04,$07,$1F,d31,0,0
; special registers
CPSR,$05,$00,$00,cpsr,0,0
FPSCR,$05,$00,$01,fpscr,0,0
SPSR,$05,$00,$02,spsr,0,0
SPSR,$05,$00,$02,spsr,0,0
APSR_nzcv,$05,$00,$03,apsr_nzcv,0,0

1
compiler/arm/rarmcon.inc
View File

@ -91,3 +91,4 @@ NR_D31 = tregister($0407001F);
NR_CPSR = tregister($05000000);
NR_FPSCR = tregister($05000001);
NR_SPSR = tregister($05000002);
NR_APSR_nzcv = tregister($05000003);

1
compiler/arm/rarmdwa.inc
View File

@ -90,4 +90,5 @@
0,
0,
0,
0,
0

2
compiler/arm/rarmnor.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armreg.dat }
92
93

3
compiler/arm/rarmnum.inc
View File

@ -90,4 +90,5 @@ tregister($0407001E),
tregister($0407001F),
tregister($05000000),
tregister($05000001),
tregister($05000002)
tregister($05000002),
tregister($05000003)

3
compiler/arm/rarmrni.inc
View File

@ -90,4 +90,5 @@
88,
89,
90,
91
91,
92

1
compiler/arm/rarmsri.inc
View File

@ -1,5 +1,6 @@
{ don't edit, this file is generated from armreg.dat }
0,
92,
89,
27,
30,

1
compiler/arm/rarmsta.inc
View File

@ -90,4 +90,5 @@
0,
0,
0,
0,
0

3
compiler/arm/rarmstd.inc
View File

@ -90,4 +90,5 @@
'd31',
'cpsr',
'fpscr',
'spsr'
'spsr',
'apsr_nzcv'

1
compiler/arm/rarmsup.inc
View File

@ -91,3 +91,4 @@ RS_D31 = $1F;
RS_CPSR = $00;
RS_FPSCR = $01;
RS_SPSR = $02;
RS_APSR_nzcv = $03;

2
compiler/avr/cpubase.pas
View File

@ -326,7 +326,7 @@ unit cpubase;
const
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i ravrstd.inc}
);

2
compiler/m68k/cpubase.pas
View File

@ -353,7 +353,7 @@ implementation
const
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i r68kstd.inc}
);

2
compiler/mips/cpubase.pas
View File

@ -295,7 +295,7 @@ unit cpubase;
const
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i rmipsstd.inc}
);

2
compiler/powerpc/cpubase.pas
View File

@ -422,7 +422,7 @@ implementation
rgbase,verbose;
const
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i rppcstd.inc}
);

2
compiler/powerpc64/cpubase.pas
View File

@ -424,7 +424,7 @@ uses
rgBase, verbose, itcpugas;
const
std_regname_table: array[tregisterindex] of string[7] = (
std_regname_table: array[tregisterindex] of string[10] = (
{$I rppcstd.inc}
);

4
compiler/x86/cpubase.pas
View File

@ -268,7 +268,7 @@ implementation
const
{$ifdef x86_64}
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i r8664std.inc}
);
@ -279,7 +279,7 @@ implementation
{$i r8664sri.inc}
);
{$else x86_64}
std_regname_table : array[tregisterindex] of string[7] = (
std_regname_table : array[tregisterindex] of string[10] = (
{$i r386std.inc}
);