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https://gitlab.com/freepascal.org/fpc/source.git
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+ added support for the shift nodes
+ added debug output on screen with -an command line option
This commit is contained in:
mazen
parent
ae3e96cdda
commit
00ee9f8063
@ -8,8 +8,15 @@ then
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cd "$COMP_DIR"
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fpc pp -gl -oppcsparc -dExtDebug -Fu"sparc;systems" -dSPARC -dNoOpt -dGDB "$1"
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fi
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if [[ "$1" != "-B" ]] || [[ "$#" -gt "1" ]]
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if [[ "$#" -gt "0" ]] && ( [[ "$1" != "-B" ]] || [[ "$#" -gt "1" ]] )
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then
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cd "$FPC_SRC_DIR/tests/sparc"
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"$COMP_DIR"/ppcsparc -s -al -Fi"$RTL_DIR"/{unix,linux,sparc,inc} -dSPARC "$@"
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if [[ "$1" == "-gdb" ]]
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then
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shift 1
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SRC_DIR=`echo "$COMP_DIR/"{,sparc,systems}":"`
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gdb -d "$SRC_DIR" --args "$COMP_DIR"/ppcsparc -s -al -Fi"$RTL_DIR"/{unix,linux,sparc,inc} -dSPARC "$@"
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else
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"$COMP_DIR"/ppcsparc -s -al -Fi"$RTL_DIR"/{unix,linux,sparc,inc} -dSPARC "$@"
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fi
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fi
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@ -149,10 +149,11 @@ implementation
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p: pchar;
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begin
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if entry then
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p := strpnew('second'+secondnames[ht]+' (entry)')
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p := strpnew('second '+secondnames[ht]+' (entry)')
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else
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p := strpnew('second'+secondnames[ht]+' (exit)');
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p := strpnew('second '+secondnames[ht]+' (exit)');
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exprasmlist.concat(tai_comment.create(p));
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WriteLn(p);
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end;
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{$endif EXTDEBUG}
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@ -332,7 +333,11 @@ implementation
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end.
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{
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$Log$
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Revision 1.39 2002-08-23 16:14:49 peter
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Revision 1.40 2002-12-21 23:21:47 mazen
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+ added support for the shift nodes
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+ added debug output on screen with -an command line option
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Revision 1.39 2002/08/23 16:14:49 peter
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* tempgen cleanup
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* tt_noreuse temp type added that will be used in genentrycode
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@ -36,10 +36,11 @@ specific processor ABI. It is overriden for each CPU target.
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LocPara : is the location where the parameter will be stored}
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procedure a_param_reg(list:TAasmOutput;size:tcgsize;r:tregister;const LocPara:TParaLocation);override;
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procedure a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST LocPara:TParaLocation);override;
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procedure a_param_ref(list:TAasmOutput;size:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation);override;
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procedure a_param_ref(list:TAasmOutput;sz:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation);override;
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procedure a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation);override;
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procedure a_call_name(list:TAasmOutput;CONST s:string);override;
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procedure a_call_ref(list:TAasmOutput;CONST ref:TReference);override;
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procedure a_call_reg(list:TAasmOutput;Reg:TRegister);override;
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{Branch Instruction}
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procedure a_jmp_always(List:TAasmOutput;l:TAsmLabel);override;
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{General purpose instyructions}
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@ -133,32 +134,32 @@ procedure tcgSPARC.a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST Loc
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InternalError(2002032213);
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end;
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END;
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procedure tcgSPARC.a_param_ref(list:TAasmOutput;size:tcgsize;const r:TReference;const LocPara:TParaLocation);
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procedure tcgSPARC.a_param_ref(list:TAasmOutput;sz:TCgSize;const r:TReference;const LocPara:TParaLocation);
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var
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ref: treference;
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tmpreg:TRegister;
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begin
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with LocPara do
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case locpara.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load_ref_reg(list,size,r,Register);
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with LocPara do
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case locpara.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load_ref_reg(list,sz,r,Register);
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LOC_REFERENCE:
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begin
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begin
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{Code conventions need the parameters being allocated in %o6+92. See
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comment on g_stack_frame}
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if locpara.sp_fixup<92
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then
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InternalError(2002081104);
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reference_reset(ref);
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ref.base:=locpara.reference.index;
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ref.offset:=locpara.reference.offset;
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tmpreg := get_scratch_reg_int(list);
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a_load_ref_reg(list,size,r,tmpreg);
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a_load_reg_ref(list,size,tmpreg,ref);
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free_scratch_reg(list,tmpreg);
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end;
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if locpara.sp_fixup<92
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then
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InternalError(2002081104);
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reference_reset(ref);
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ref.base:=locpara.reference.index;
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ref.offset:=locpara.reference.offset;
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tmpreg := get_scratch_reg_int(list);
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a_load_ref_reg(list,sz,r,tmpreg);
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a_load_reg_ref(list,sz,tmpreg,ref);
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free_scratch_reg(list,tmpreg);
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end;
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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case size of
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case sz of
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OS_32:
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a_loadfpu_ref_reg(list,OS_F32,r,locpara.register);
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OS_64:
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@ -205,10 +206,18 @@ procedure tcgSPARC.a_call_name(list:TAasmOutput;CONST s:string);
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END;
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END;
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procedure tcgSPARC.a_call_ref(list:TAasmOutput;CONST ref:TReference);
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BEGIN
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begin
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list.concat(taicpu.op_ref(A_CALL,ref));
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list.concat(taicpu.op_none(A_NOP));
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END;
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end;
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procedure TCgSparc.a_call_reg(list:TAasmOutput;Reg:TRegister);
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begin
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list.concat(taicpu.op_reg(A_JMPL,reg));
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if target_info.system=system_sparc_linux
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then
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list.concat(taicpu.op_none(A_NOP));
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procinfo.flags:=procinfo.flags or pi_do_call;
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end;
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{********************** branch instructions ********************}
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procedure TCgSPARC.a_jmp_always(List:TAasmOutput;l:TAsmLabel);
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begin
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@ -247,13 +256,45 @@ procedure tcgSPARC.a_load_reg_ref(list:TAasmOutput;size:TCGSize;reg:tregister;CO
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BEGIN
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list.concat(taicpu.op_reg_ref(A_ST,reg,ref));
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END;
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procedure tcgSPARC.a_load_ref_reg(list:TAasmOutput;size:tcgsize;const ref:TReference;reg:tregister);
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procedure tcgSPARC.a_load_ref_reg(list:TAasmOutput;size:TCgSize;const ref:TReference;reg:tregister);
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var
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op:tasmop;
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s:topsize;
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begin
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sizes2load(size,S_SW,op,s);
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list.concat(taicpu.op_ref_reg(op,ref,reg));
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case size of
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{ signed integer registers }
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OS_S8:
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Op:=A_LDSB;{Load Signed Byte}
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OS_S16:
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Op:=A_LDSH;{Load Signed Halfword}
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OS_S32:
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Op:=A_LD;{Load Word}
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OS_S64:
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Op:=A_LDD;{Load Double Word}
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{ unsigned integer registers }
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//A_LDSTUB;{Load-Store Unsigned Byte}
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OS_8:
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Op:=A_LDUB;{Load Unsigned Bye}
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OS_16:
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Op:=A_LDUH;{Load Unsigned Halfword}
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OS_32:
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Op:=A_LD;{Load Word}
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OS_64:
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Op:=A_LDD;{Load Double Word}
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{ floating-point real registers }
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OS_F32:
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Op:=A_LDF;{Load Floating-point word}
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//A_LDFSR
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OS_F64:
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Op:=A_LDDF;{Load Double Floating-point word}
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//A_LDC;{Load Coprocessor}
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//A_LDCSR;
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//A_LDDC;{Load Double Coprocessor}
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else
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InternalError(2002122100);
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end;
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with list do
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concat(taicpu.op_ref_reg(op,ref,reg));
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end;
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procedure tcgSPARC.a_load_reg_reg(list:TAasmOutput;fromsize,tosize:tcgsize;reg1,reg2:tregister);
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var
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@ -761,18 +802,17 @@ procedure tcgSPARC.a_cmp_const_ref_label(list:TAasmOutput;size:tcgsize;cmp_op:to
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a_jmp_cond(list,cmp_op,l);}
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end;
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procedure tcgSPARC.a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);
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var
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opsize:topsize;
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begin
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opsize := S_Q{makeregsize(reg,size)};
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list.concat(taicpu.op_ref_reg(A_CMP,ref,reg));
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a_jmp_cond(list,cmp_op,l);
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end;
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procedure tcgSPARC.a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);
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procedure tcgSPARC.a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);
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var
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TempReg:TRegister;
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begin
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TempReg:=cg.get_scratch_reg_int(List);
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a_load_ref_reg(list,OS_32,Ref,TempReg);
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list.concat(taicpu.op_reg_reg(A_SUBcc,TempReg,Reg));
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a_jmp_cond(list,cmp_op,l);
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cg.free_scratch_reg(exprasmlist,TempReg);
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end;
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procedure tcgSPARC.a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);
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var
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ai:taicpu;
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@ -1283,7 +1323,11 @@ BEGIN
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END.
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{
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$Log$
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Revision 1.26 2002-11-25 19:21:49 mazen
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Revision 1.27 2002-12-21 23:21:47 mazen
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+ added support for the shift nodes
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+ added debug output on screen with -an command line option
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Revision 1.26 2002/11/25 19:21:49 mazen
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* fixed support of nSparcInline
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Revision 1.25 2002/11/25 17:43:28 peter
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@ -28,14 +28,18 @@ the behaviour of such a unit having just a USES clause!}
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implementation
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uses
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ncgbas,ncgflw,ncgcnv,ncgld,ncgmem,ncgcon,{ncgset,}
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naddcpu,ncpucall,{n386con,n386cnv,n386flw,n386mat,n386mem,}
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ncpuadd,ncpucall,{n386con,n386cnv,n386flw,}ncpumat,{n386mem,}
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{n386set,}ncpuinln,{n386opt,}ncpucnv,
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{ this not really a node }
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{nSPARCobj,}rgcpu;
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{ncpuobj,}rgcpu;
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end.
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{
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$Log$
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Revision 1.5 2002-11-30 20:03:29 mazen
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Revision 1.6 2002-12-21 23:21:47 mazen
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+ added support for the shift nodes
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+ added debug output on screen with -an command line option
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Revision 1.5 2002/11/30 20:03:29 mazen
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+ ncpuinln node
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}
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@ -65,18 +65,19 @@ procedure TSparcprocinfo.after_header;
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receive the return value of the called function}
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Return_Offset:=64;{16*4}
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procdef.parast.address_fixup:=(16+1)*4;
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{Reserve the stack for copying parameters passed into registers. By default
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we reserve space for the 6 input registers even if the function had less
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parameters.}
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procdef.localst.address_fixup:=6*4+(16+1)*4;
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end;
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procedure TSparcProcInfo.after_pass1;
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begin
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with ProcDef do
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begin
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{Reserve the stack for copying parameters passed into registers. By
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default we reserve space for the 6 input registers if the function had
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less parameters. Otherwise, we allocate data sizeof parameters}
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if parast.datasize>6*4
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then
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localst.address_fixup:=parast.address_fixup+parast.datasize;
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localst.address_fixup:=parast.address_fixup+parast.datasize
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else
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procdef.localst.address_fixup:=parast.address_fixup+6*4;
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firsttemp_offset:=localst.address_fixup+localst.datasize;
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WriteLn('Parameter copies start at: %i6+'+tostr(parast.address_fixup));
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WriteLn('Locals start at: %o6+'+tostr(localst.address_fixup));
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@ -93,7 +94,11 @@ begin
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end.
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{
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$Log$
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Revision 1.8 2002-11-17 17:49:09 mazen
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Revision 1.9 2002-12-21 23:21:47 mazen
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+ added support for the shift nodes
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+ added debug output on screen with -an command line option
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Revision 1.8 2002/11/17 17:49:09 mazen
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+ return_result_reg and function_result_reg are now used, in all plateforms, to pass functions result between called function and its caller. See the explanation of each one
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Revision 1.7 2002/11/14 21:42:08 mazen
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@ -19,7 +19,7 @@
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************}
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UNIT naddcpu;
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UNIT ncpuadd;
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{$INCLUDE fpcdefs.inc}
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INTERFACE
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USES
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@ -408,7 +408,11 @@ begin
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end.
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{
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$Log$
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Revision 1.10 2002-11-25 17:43:28 peter
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Revision 1.1 2002-12-21 23:21:47 mazen
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+ added support for the shift nodes
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+ added debug output on screen with -an command line option
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Revision 1.10 2002/11/25 17:43:28 peter
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* splitted defbase in defutil,symutil,defcmp
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* merged isconvertable and is_equal into compare_defs(_ext)
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* made operator search faster by walking the list only once
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