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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-06-24 22:58:18 +02:00
Fix for bug report 38549 about wrong code generation
for mips/mipsel and riscv32/riscv64 CPUs for set operators '<=' and '>='. New tests for this bug report. tw38549.pp, main source, also included by tw38549a.pp, tw38549b.pp, tw38459c.pp and tw38459d.pp with explicit {$packset X}, with X=1,2,4, or 8 added. git-svn-id: trunk@48874 -
This commit is contained in:
parent
01937c4630
commit
01a351f804
5
.gitattributes
vendored
5
.gitattributes
vendored
@ -18678,6 +18678,11 @@ tests/webtbs/tw38413.pp svneol=native#text/pascal
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tests/webtbs/tw38429.pp svneol=native#text/pascal
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tests/webtbs/tw38429.pp svneol=native#text/pascal
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tests/webtbs/tw38497.pp svneol=native#text/pascal
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tests/webtbs/tw38497.pp svneol=native#text/pascal
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tests/webtbs/tw38527.pp svneol=native#text/plain
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tests/webtbs/tw38527.pp svneol=native#text/plain
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tests/webtbs/tw38549.pp svneol=native#text/plain
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tests/webtbs/tw38549a.pp svneol=native#text/plain
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tests/webtbs/tw38549b.pp svneol=native#text/plain
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tests/webtbs/tw38549c.pp svneol=native#text/plain
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tests/webtbs/tw38549d.pp svneol=native#text/plain
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tests/webtbs/tw3863.pp svneol=native#text/plain
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tests/webtbs/tw3863.pp svneol=native#text/plain
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tests/webtbs/tw3864.pp svneol=native#text/plain
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tests/webtbs/tw3864.pp svneol=native#text/plain
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tests/webtbs/tw3865.pp svneol=native#text/plain
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tests/webtbs/tw3865.pp svneol=native#text/plain
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@ -36,7 +36,7 @@ type
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private
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private
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procedure cmp64_lt(left_reg, right_reg: TRegister64;unsigned:boolean);
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procedure cmp64_lt(left_reg, right_reg: TRegister64;unsigned:boolean);
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procedure cmp64_le(left_reg, right_reg: TRegister64;unsigned:boolean);
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procedure cmp64_le(left_reg, right_reg: TRegister64;unsigned:boolean);
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procedure second_generic_cmp32(unsigned: boolean);
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procedure second_generic_cmp32(unsigned,is_smallset: boolean);
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procedure second_mul64bit;
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procedure second_mul64bit;
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protected
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protected
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procedure second_addfloat; override;
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procedure second_addfloat; override;
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@ -72,18 +72,31 @@ uses
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tmipsaddnode
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tmipsaddnode
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*****************************************************************************}
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*****************************************************************************}
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procedure tmipsaddnode.second_generic_cmp32(unsigned: boolean);
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procedure tmipsaddnode.second_generic_cmp32(unsigned,is_smallset: boolean);
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var
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var
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cond: TOpCmp;
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cond: TOpCmp;
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allow_constant : boolean;
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dreg : tregister;
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begin
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begin
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pass_left_right;
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pass_left_right;
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force_reg_left_right(True, True);
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allow_constant:=(not is_smallset) or not (nodetype in [lten,gten]);
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force_reg_left_right(True, allow_constant);
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location_reset(location,LOC_FLAGS,OS_NO);
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location_reset(location,LOC_FLAGS,OS_NO);
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cond:=cmpnode2topcmp(unsigned);
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cond:=cmpnode2topcmp(unsigned);
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if nf_swapped in flags then
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if nf_swapped in flags then
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cond:=swap_opcmp(cond);
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cond:=swap_opcmp(cond);
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if is_smallset and (nodetype in [lten,gten]) then
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begin
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if ((nodetype=lten) and not (nf_swapped in flags)) or
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((nodetype=gten) and (nf_swapped in flags)) then
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dreg:=right.location.register
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else
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dreg:=left.location.register;
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_AND,dreg,right.location.register,left.location.register));
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cond:=OC_EQ;
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end;
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location.resflags.cond:=cond;
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location.resflags.cond:=cond;
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location.resflags.reg1:=left.location.register;
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location.resflags.reg1:=left.location.register;
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location.resflags.use_const:=(right.location.loc=LOC_CONSTANT);
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location.resflags.use_const:=(right.location.loc=LOC_CONSTANT);
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@ -304,13 +317,13 @@ end;
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procedure tmipsaddnode.second_cmpboolean;
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procedure tmipsaddnode.second_cmpboolean;
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begin
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begin
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second_generic_cmp32(true);
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second_generic_cmp32(true,false);
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end;
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end;
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procedure tmipsaddnode.second_cmpsmallset;
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procedure tmipsaddnode.second_cmpsmallset;
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begin
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begin
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second_generic_cmp32(true);
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second_generic_cmp32(true,true);
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end;
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end;
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@ -319,7 +332,7 @@ var
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unsigned: boolean;
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unsigned: boolean;
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begin
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begin
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unsigned := not (is_signed(left.resultdef)) or not (is_signed(right.resultdef));
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unsigned := not (is_signed(left.resultdef)) or not (is_signed(right.resultdef));
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second_generic_cmp32(unsigned);
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second_generic_cmp32(unsigned,false);
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end;
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end;
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@ -34,7 +34,7 @@ unit nrvadd;
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trvaddnode = class(tcgaddnode)
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trvaddnode = class(tcgaddnode)
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function pass_1: tnode; override;
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function pass_1: tnode; override;
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protected
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protected
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procedure Cmp(signed: boolean);
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procedure Cmp(signed,is_smallset: boolean);
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function use_mul_helper: boolean; override;
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function use_mul_helper: boolean; override;
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@ -72,14 +72,17 @@ implementation
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low_value = {$ifdef CPU64BITALU} low(int64) {$else} low(longint) {$endif};
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low_value = {$ifdef CPU64BITALU} low(int64) {$else} low(longint) {$endif};
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{$endif}
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{$endif}
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procedure trvaddnode.Cmp(signed: boolean);
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procedure trvaddnode.Cmp(signed,is_smallset: boolean);
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var
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var
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flabel,tlabel: tasmlabel;
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flabel,tlabel: tasmlabel;
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op, opi: TAsmOp;
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op, opi: TAsmOp;
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allow_constant : boolean;
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begin
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begin
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pass_left_right;
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pass_left_right;
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force_reg_left_right(true,true);
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allow_constant:=(not is_smallset) or not (nodetype in [lten,gten]);
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force_reg_left_right(true,allow_constant);
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if nf_swapped in flags then
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if nf_swapped in flags then
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swapleftright;
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swapleftright;
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@ -164,13 +167,21 @@ implementation
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if (left.location.loc=LOC_CONSTANT) and
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if (left.location.loc=LOC_CONSTANT) and
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(not is_imm12(left.location.value)) then
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(not is_imm12(left.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if is_smallset then
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begin
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_AND,right.location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_SUB,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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end
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else
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begin
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if left.location.loc=LOC_CONSTANT then
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if left.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,right.location.register,left.location.value))
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,right.location.register,left.location.value))
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else
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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end;
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end;
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end;
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gten:
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gten:
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begin
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begin
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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@ -179,13 +190,21 @@ implementation
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if (right.location.loc=LOC_CONSTANT) and
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if (right.location.loc=LOC_CONSTANT) and
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(not is_imm12(right.location.value)) then
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(not is_imm12(right.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if is_smallset then
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begin
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_AND,left.location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_SUB,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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end
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else
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begin
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if right.location.loc=LOC_CONSTANT then
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if right.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,left.location.register,right.location.value))
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,left.location.register,right.location.value))
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else
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTIU,location.register,location.register,1));
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end;
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end;
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end;
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else
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else
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Internalerror(2016061101);
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Internalerror(2016061101);
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end;
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end;
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@ -205,7 +224,7 @@ implementation
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procedure trvaddnode.second_cmpsmallset;
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procedure trvaddnode.second_cmpsmallset;
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begin
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begin
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Cmp(true);
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Cmp(false,true);
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end;
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end;
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@ -216,7 +235,7 @@ implementation
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unsigned:=not(is_signed(left.resultdef)) or
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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not(is_signed(right.resultdef));
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Cmp(not unsigned);
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Cmp(not unsigned,false);
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end;
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end;
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@ -227,7 +246,7 @@ implementation
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unsigned:=not(is_signed(left.resultdef)) or
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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not(is_signed(right.resultdef));
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Cmp(not unsigned);
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Cmp(not unsigned,false);
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end;
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end;
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226
tests/webtbs/tw38549.pp
Normal file
226
tests/webtbs/tw38549.pp
Normal file
@ -0,0 +1,226 @@
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type
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{$ifdef SET_39}
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{$define SET_31}
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{$endif}
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{$ifdef SET_31}
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{$define SET_25}
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{$endif}
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{$ifdef SET_25}
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{$define SET_23}
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{$endif}
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{$ifdef SET_23}
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{$define SET_17}
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{$endif}
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{$ifdef SET_17}
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{$define SET_15}
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{$endif}
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{$ifdef SET_15}
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{$define SET_9}
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{$endif}
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{ options for symtables }
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tsymtableoption = (
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sto_has_helper, { contains at least one helper symbol }
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sto_has_generic, { contains at least one generic symbol }
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sto_has_operator, { contains at least one operator overload }
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sto_needs_init_final, { the symtable needs initialization and/or
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finalization of variables/constants }
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sto_has_non_trivial_init, { contains at least on managed type that is not
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initialized to zero (e.g. a record with management
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operators }
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sto_above
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{$ifdef SET_9}
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,sto_6
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,sto_7
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,sto_8
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,sto_9
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{$endif}
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{$ifdef SET_15}
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,sto_10
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,sto_11
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,sto_12
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,sto_13
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,sto_14
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,sto_15
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{$endif}
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{$ifdef SET_17}
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,sto_16
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,sto_17
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{$endif}
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{$ifdef SET_23}
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,sto_18
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,sto_19
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,sto_20
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,sto_21
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,sto_22
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,sto_23
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{$endif}
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{$ifdef SET_25}
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,sto_24
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,sto_25
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{$endif}
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{$ifdef SET_31}
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,sto_26
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,sto_27
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,sto_28
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,sto_29
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,sto_30
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,sto_31
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{$endif}
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{$ifdef SET_39}
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,sto_32
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,sto_33
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,sto_34
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,sto_35
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,sto_36
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,sto_37
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,sto_38
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,sto_39
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{$endif}
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);
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tsymtableoptions = set of tsymtableoption;
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const
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ok_count : longint = 0;
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error_count : longint = 0;
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procedure add_error;
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begin
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writeln('New error');
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inc(error_count);
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end;
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procedure test(tableoptions : tsymtableoptions; expected : boolean);
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begin
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if [sto_needs_init_final,sto_has_non_trivial_init] <= tableoptions then
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begin
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if expected then
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begin
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writeln('Ok');
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inc(ok_count);
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end
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else
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add_error;
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end
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else
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begin
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if not expected then
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begin
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writeln('Ok');
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inc(ok_count);
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end
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else
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add_error;
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end;
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if tableoptions >= [sto_needs_init_final,sto_has_non_trivial_init] then
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begin
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if expected then
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begin
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writeln('Ok');
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inc(ok_count);
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end
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else
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add_error;
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end
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else
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begin
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if not expected then
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begin
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writeln('Ok');
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inc(ok_count);
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end
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else
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add_error;
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end
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end;
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procedure test2(tableoptions1, tableoptions2 : tsymtableoptions; expected : boolean);
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|
begin
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|
if tableoptions1 <= tableoptions2 then
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begin
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|
if expected then
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begin
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writeln('Ok');
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inc(ok_count);
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end
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else
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add_error;
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|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if not expected then
|
||||||
|
begin
|
||||||
|
writeln('Ok');
|
||||||
|
inc(ok_count);
|
||||||
|
end
|
||||||
|
else
|
||||||
|
add_error;
|
||||||
|
end
|
||||||
|
end;
|
||||||
|
|
||||||
|
var
|
||||||
|
tableoptions1, tableoptions2 : tsymtableoptions;
|
||||||
|
|
||||||
|
begin
|
||||||
|
tableoptions1:=[];
|
||||||
|
test(tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_helper];
|
||||||
|
test(tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_needs_init_final];
|
||||||
|
test(tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_non_trivial_init];
|
||||||
|
test(tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
test(tableoptions1,true);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_helper,sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
test(tableoptions1,true);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_helper,sto_needs_init_final,sto_has_non_trivial_init,sto_above];
|
||||||
|
test(tableoptions1,true);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_helper,sto_has_non_trivial_init,sto_above];
|
||||||
|
test(tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[];
|
||||||
|
tableoptions2:=[];
|
||||||
|
test2(tableoptions1,tableoptions2,true);
|
||||||
|
test2(tableoptions2,tableoptions1,true);
|
||||||
|
|
||||||
|
tableoptions2:=[sto_has_helper];
|
||||||
|
test2(tableoptions1,tableoptions2,true);
|
||||||
|
test2(tableoptions2,tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
tableoptions2:=[sto_needs_init_final,sto_has_non_trivial_init,sto_has_helper];
|
||||||
|
test2(tableoptions1,tableoptions2,true);
|
||||||
|
test2(tableoptions2,tableoptions1,false);
|
||||||
|
test2(tableoptions1,tableoptions1,true);
|
||||||
|
test2(tableoptions2,tableoptions2,true);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
tableoptions2:=[sto_has_helper,sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
test2(tableoptions1,tableoptions2,true);
|
||||||
|
test2(tableoptions2,tableoptions1,false);
|
||||||
|
|
||||||
|
tableoptions1:=[sto_has_helper,sto_needs_init_final,sto_has_non_trivial_init];
|
||||||
|
tableoptions2:=[sto_needs_init_final,sto_has_non_trivial_init,sto_above];
|
||||||
|
test2(tableoptions1,tableoptions2,false);
|
||||||
|
test2(tableoptions2,tableoptions1,false);
|
||||||
|
|
||||||
|
writeln('Test for sets of size : ',sizeof(tableoptions1));
|
||||||
|
if error_count > 0 then
|
||||||
|
begin
|
||||||
|
writeln(error_count,' test(s) failed');
|
||||||
|
writeln(ok_count,' test(s) OK');
|
||||||
|
halt(1);
|
||||||
|
end
|
||||||
|
else
|
||||||
|
writeln('Test OK: ',ok_count);
|
||||||
|
end.
|
||||||
|
|
5
tests/webtbs/tw38549a.pp
Normal file
5
tests/webtbs/tw38549a.pp
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
{$packset 1}
|
||||||
|
|
||||||
|
{$i tw38549.pp}
|
||||||
|
|
5
tests/webtbs/tw38549b.pp
Normal file
5
tests/webtbs/tw38549b.pp
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
{$packset 2}
|
||||||
|
|
||||||
|
{$i tw38549.pp}
|
||||||
|
|
5
tests/webtbs/tw38549c.pp
Normal file
5
tests/webtbs/tw38549c.pp
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
{$packset 4}
|
||||||
|
|
||||||
|
{$i tw38549.pp}
|
||||||
|
|
5
tests/webtbs/tw38549d.pp
Normal file
5
tests/webtbs/tw38549d.pp
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
{$packset 8}
|
||||||
|
|
||||||
|
{$i tw38549.pp}
|
||||||
|
|
Loading…
Reference in New Issue
Block a user