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https://gitlab.com/freepascal.org/fpc/source.git
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* ARM compiler compiles again
This commit is contained in:
florian
parent
ed7610985b
commit
024d08e05a
@ -69,14 +69,14 @@ uses
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function is_nop: boolean; override;
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function is_move:boolean; override;
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function spill_registers(list:Taasmoutput;
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rgget:Trggetproc;
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rgunget:Trgungetproc;
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r:tsuperregisterset;
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var unusedregsint:tsuperregisterset;
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const spilltemplist:Tspill_temp_list):boolean; override;
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end;
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{ register spilling code }
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function spilling_decode_loadstore(op: tasmop; var counterpart: tasmop; var wasload: boolean): boolean;override;
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function spilling_create_loadstore(op: tasmop; r:tregister; const ref:treference): tai;override;
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function spilling_create_load(const ref:treference;r:tregister): tai;override;
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function spilling_create_store(r:tregister; const ref:treference): tai;override;
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end;
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tai_align = class(tai_align_abstract)
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{ nothing to add }
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end;
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@ -247,16 +247,6 @@ implementation
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end;
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constructor taicpu.op_const_const_sym(op : tasmop;_op1,_op2 : longint; _op3: tasmsymbol);
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begin
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inherited create(op);
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ops:=3;
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loadconst(0,aword(_op1));
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loadconst(1,aword(_op2));
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loadsymbol(2,_op3,0);
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end;
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constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
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begin
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inherited create(op);
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@ -306,278 +296,38 @@ implementation
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end;
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function taicpu.spill_registers(list:Taasmoutput;
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rgget:Trggetproc;
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rgunget:Trgungetproc;
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r:tsuperregisterset;
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var unusedregsint:tsuperregisterset;
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const spilltemplist:Tspill_temp_list): boolean;
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function get_insert_pos(p:Tai;huntfor1,huntfor2,huntfor3:Tsuperregister):Tai;
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var back:tsuperregisterset;
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function taicpu.spilling_decode_loadstore(op: tasmop; var counterpart: tasmop; var wasload: boolean): boolean;
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begin
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back:=unusedregsint;
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get_insert_pos:=p;
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while (p<>nil) and (p.typ=ait_regalloc) do
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begin
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{Rewind the register allocation.}
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if Tai_regalloc(p).allocation then
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include(unusedregsint,Tai_regalloc(p).reg.number shr 8)
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else
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begin
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exclude(unusedregsint,Tai_regalloc(p).reg.number shr 8);
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if Tai_regalloc(p).reg.number shr 8=huntfor1 then
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begin
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get_insert_pos:=Tai(p.previous);
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back:=unusedregsint;
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end;
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if Tai_regalloc(p).reg.number shr 8=huntfor2 then
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begin
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get_insert_pos:=Tai(p.previous);
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back:=unusedregsint;
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end;
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if Tai_regalloc(p).reg.number shr 8=huntfor3 then
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begin
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get_insert_pos:=Tai(p.previous);
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back:=unusedregsint;
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end;
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end;
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p:=Tai(p.previous);
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end;
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unusedregsint:=back;
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end;
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procedure forward_allocation(p:Tai);
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begin
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{Forward the register allocation again.}
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while (p<>self) do
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begin
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if p.typ<>ait_regalloc then
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internalerror(200305311);
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if Tai_regalloc(p).allocation then
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exclude(unusedregsint,Tai_regalloc(p).reg.number shr 8)
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else
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include(unusedregsint,Tai_regalloc(p).reg.number shr 8);
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p:=Tai(p.next);
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end;
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end;
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function decode_loadstore(op: tasmop; var counterpart: tasmop; wasload: boolean): boolean;
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begin
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result := true;
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wasload := true;
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case op of
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A_LDR:
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begin
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counterpart := A_STR;
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end;
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A_LDM:
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internalerror(2003070602);
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else
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result := false;
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end;
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end;
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var i:byte;
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supreg, reg1, reg2, reg3: Tsuperregister;
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helpreg:Tregister;
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helpins:Taicpu;
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op:Tasmop;
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pos:Tai;
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wasload: boolean;
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begin
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spill_registers:=false;
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if (ops = 2) and
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(oper[1].typ=top_ref) and
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{ oper[1] can also be ref in case of "lis r3,symbol@ha" or so }
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decode_loadstore(opcode,op,wasload) then
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begin
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{ the register that's being stored/loaded }
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supreg:=oper[0].reg.number shr 8;
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if supreg in r then
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begin
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// Example:
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// l?? r20d, 8(r1) ; r20d must be spilled into -60(r1)
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//
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// Change into:
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//
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// l?? r21d, 8(r1)
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// st? r21d, -60(r1)
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//
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// And:
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//
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// st? r20d, 8(r1) ; r20d must be spilled into -60(r1)
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//
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// Change into:
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//
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// l?? r21d, -60(r1)
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// st? r21d, 8(r1)
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pos := get_insert_pos(Tai(previous),oper[0].reg.number shr 8,
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oper[1].ref^.base.number shr 8,oper[1].ref^.index.number shr 8);
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rgget(list,pos,0,helpreg);
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spill_registers := true;
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if wasload then
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begin
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helpins := taicpu.op_reg_ref(opcode,helpreg,oper[1].ref^);
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loadref(1,spilltemplist[supreg]);
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opcode := op;
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end
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else
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helpins := taicpu.op_reg_ref(op,helpreg,spilltemplist[supreg]);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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loadreg(0,helpreg);
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rgunget(list,helpins,helpreg);
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forward_allocation(tai(helpins.next));
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{$ifdef debugra}
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writeln('spilling!');
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list.insertafter(tai_comment.Create(strpnew('Spilling!')),helpins);
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{$endif debugra}
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end;
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{ now the registers used in the reference }
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{ a) base }
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supreg := oper[1].ref^.base.number shr 8;
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if supreg in r then
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begin
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if wasload then
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pos:=get_insert_pos(Tai(previous),oper[1].ref^.index.number shr 8,oper[0].reg.number shr 8,0)
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else
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pos:=get_insert_pos(Tai(previous),oper[1].ref^.index.number shr 8,0,0);
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rgget(list,pos,0,helpreg);
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spill_registers:=true;
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helpins:=Taicpu.op_reg_ref(A_LDR,helpreg,spilltemplist[supreg]);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[1].ref^.base:=helpreg;
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rgunget(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next));
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{$ifdef debugra}
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writeln('spilling!');
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list.insertafter(tai_comment.Create(strpnew('Spilling!')),helpins);
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{$endif debugra}
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end;
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{ b) index }
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supreg := oper[1].ref^.index.number shr 8;
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if supreg in r then
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begin
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if wasload then
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pos:=get_insert_pos(Tai(previous),oper[1].ref^.base.number shr 8,oper[0].reg.number shr 8,0)
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else
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pos:=get_insert_pos(Tai(previous),oper[1].ref^.base.number shr 8,0,0);
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rgget(list,pos,0,helpreg);
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spill_registers:=true;
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helpins:=Taicpu.op_reg_ref(A_LDR,helpreg,spilltemplist[supreg]);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[1].ref^.index:=helpreg;
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rgunget(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next));
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{$ifdef debugra}
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writeln('spilling!');
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list.insertafter(tai_comment.Create(strpnew('Spilling!')),helpins);
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{$endif debugra}
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end;
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{ load/store is done }
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exit;
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end;
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{ all other instructions the compiler generates are the same (I hope): }
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{ operand 0 is a register and is the destination, the others are sources }
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{ and can be either registers or constants }
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{ exception: branches (is_jmp isn't always set for them) }
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if oper[0].typ <> top_reg then
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exit;
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reg1 := oper[0].reg.number shr 8;
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if oper[1].typ = top_reg then
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reg2 := oper[1].reg.number shr 8
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else
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reg2 := 0;
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if (ops >= 3) and
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(oper[2].typ = top_reg) then
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reg3 := oper[2].reg.number shr 8
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else
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reg3 := 0;
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supreg:=reg1;
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if supreg in r then
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begin
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// Example:
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// add r20d, r21d, r22d ; r20d must be spilled into -60(r1)
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//
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// Change into:
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//
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// lwz r23d, -60(r1)
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// add r23d, r21d, r22d
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// stw r23d, -60(r1)
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pos := get_insert_pos(Tai(previous),reg1,reg2,reg3);
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rgget(list,pos,0,helpreg);
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spill_registers := true;
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helpins := taicpu.op_reg_ref(A_STR,helpreg,spilltemplist[supreg]);
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list.insertafter(helpins,self);
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helpins := taicpu.op_reg_ref(A_LDR,helpreg,spilltemplist[supreg]);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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loadreg(0,helpreg);
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rgunget(list,helpins,helpreg);
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forward_allocation(tai(helpins.next));
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{$ifdef debugra}
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writeln('spilling!');
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list.insertafter(tai_comment.Create(strpnew('Spilling!')),helpins);
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{$endif debugra}
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end;
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for i := 1 to 2 do
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if (oper[i].typ = top_reg) then
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result := true;
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wasload := true;
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case op of
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A_LDR:
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begin
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supreg:=oper[i].reg.number;
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if supreg in r then
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begin
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// Example:
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// add r20d, r21d, r22d ; r20d must be spilled into -60(r1)
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//
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// Change into:
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//
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// lwz r23d, -60(r1)
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// add r23d, r21d, r22d
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// stw r23d, -60(r1)
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pos := get_insert_pos(Tai(previous),reg1,reg2,reg3);
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rgget(list,pos,0,helpreg);
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spill_registers := true;
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helpins := taicpu.op_reg_ref(A_LDR,helpreg,spilltemplist[supreg]);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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loadreg(i,helpreg);
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rgunget(list,helpins,helpreg);
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forward_allocation(tai(helpins.next));
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{$ifdef debugra}
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writeln('spilling!');
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list.insertafter(tai_comment.Create(strpnew('Spilling!')),helpins);
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{$endif debugra}
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end;
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counterpart := A_STR;
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end;
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A_LDM:
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internalerror(2003070602);
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else
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result := false;
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end;
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end;
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function taicpu.spilling_create_loadstore(op: tasmop; r:tregister; const ref:treference): tai;
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begin
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result:=taicpu.op_reg_ref(opcode,r,ref);
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end;
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function taicpu.spilling_create_load(const ref:treference;r:tregister): tai;
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begin
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result:=taicpu.op_reg_ref(A_LDR,r,ref);
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end;
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function taicpu.spilling_create_store(r:tregister; const ref:treference): tai;
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begin
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result:=taicpu.op_reg_ref(A_STR,r,ref);
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end;
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@ -615,7 +365,10 @@ implementation
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end.
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{
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$Log$
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Revision 1.9 2003-09-04 00:15:29 florian
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Revision 1.10 2003-09-04 21:07:03 florian
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* ARM compiler compiles again
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Revision 1.9 2003/09/04 00:15:29 florian
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* first bunch of adaptions of arm compiler for new register type
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Revision 1.8 2003/09/03 11:18:37 florian
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@ -85,8 +85,8 @@ unit cgcpu;
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procedure g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef); override;
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procedure g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
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procedure g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
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procedure g_save_standard_registers(list : taasmoutput; usedinproc : tsuperregisterset);override;
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procedure g_restore_standard_registers(list : taasmoutput; usedinproc : tsuperregisterset);override;
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procedure g_save_all_registers(list : taasmoutput);override;
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procedure g_restore_all_registers(list : taasmoutput;accused,acchiused:boolean);override;
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@ -206,9 +206,7 @@ unit cgcpu;
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var
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r : tregister;
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begin
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r.enum:=R_INTREGISTER;
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r.number:=NR_PC;
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list.concat(taicpu.op_reg_reg(A_MOV,r,reg));
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list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,reg));
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if not(pi_do_call in current_procinfo.flags) then
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internalerror(2003060704);
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end;
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@ -218,9 +216,7 @@ unit cgcpu;
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var
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r : tregister;
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begin
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r.enum:=R_INTREGISTER;
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r.number:=NR_PC;
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a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,r);
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a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_PC);
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if not(pi_do_call in current_procinfo.flags) then
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internalerror(2003060705);
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end;
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@ -348,9 +344,9 @@ unit cgcpu;
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OP_MUL:
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begin
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{ the arm doesn't allow that rd and rm are the same }
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if dst.number=src2.number then
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if dst=src2 then
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begin
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if src1.number<>src2.number then
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if src1<>src2 then
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list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2))
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else
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begin
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@ -420,16 +416,15 @@ unit cgcpu;
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tmpref : treference;
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l : tasmlabel;
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begin
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tmpreg.enum:=R_INTREGISTER;
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tmpreg.number:=NR_NO;
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tmpreg:=NR_NO;
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{ Be sure to have a base register }
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if (ref.base.number=NR_NO) then
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if (ref.base=NR_NO) then
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begin
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if ref.shiftmode<>SM_None then
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internalerror(200308294);
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ref.base:=ref.index;
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ref.index.number:=NR_NO;
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ref.index:=NR_NO;
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end;
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{ absolute symbols can't be handled directly, we've to store the symbol reference
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@ -464,13 +459,12 @@ unit cgcpu;
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tmpreg:=rg.getregisterint(list,OS_INT);
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reference_reset(tmpref);
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tmpref.symbol:=l;
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tmpref.base.enum:=R_INTREGISTER;
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tmpref.base.number:=NR_R15;
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tmpref.base:=NR_R15;
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list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
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if (ref.base.number<>NR_NO) then
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if (ref.base<>NR_NO) then
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begin
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if ref.index.number<>NR_NO then
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if ref.index<>NR_NO then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
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rg.ungetregister(list,ref.base);
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@ -490,7 +484,7 @@ unit cgcpu;
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ref.symbol:=nil;
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end;
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list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix));
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if (tmpreg.number<>NR_NO) then
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if (tmpreg<>NR_NO) then
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rg.ungetregisterint(list,tmpreg);
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end;
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@ -547,11 +541,7 @@ unit cgcpu;
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so : tshifterop;
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begin
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shifterop_reset(so);
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if (reg1.enum<>R_INTREGISTER) or (reg1.number = 0) then
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internalerror(200303101);
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if (reg2.enum<>R_INTREGISTER) or (reg2.number = 0) then
|
||||
internalerror(200303102);
|
||||
if (reg1.number<>reg2.number) or
|
||||
if (reg1<>reg2) or
|
||||
(tcgsize2size[tosize] < tcgsize2size[fromsize]) or
|
||||
((tcgsize2size[tosize] = tcgsize2size[fromsize]) and
|
||||
(tosize <> fromsize) and
|
||||
@ -649,24 +639,19 @@ unit cgcpu;
|
||||
tmpreg : tregister;
|
||||
b : byte;
|
||||
begin
|
||||
if reg.enum=R_INTREGISTER then
|
||||
begin
|
||||
if is_shifter_const(a,b) then
|
||||
list.concat(taicpu.op_reg_const(A_CMN,reg,a))
|
||||
{ CMN reg,0 and CMN reg,$80000000 are different from CMP reg,$ffffffff
|
||||
and CMP reg,$7fffffff regarding the flags according to the ARM manual }
|
||||
else if is_shifter_const(not(a),b) and (a<>$7fffffff) and (a<>$ffffffff) then
|
||||
list.concat(taicpu.op_reg_const(A_CMN,reg,not(a)))
|
||||
else
|
||||
begin
|
||||
tmpreg:=rg.getregisterint(list,size);
|
||||
a_load_const_reg(list,size,a,tmpreg);
|
||||
list.concat(taicpu.op_reg_reg(A_CMP,reg,tmpreg));
|
||||
rg.ungetregisterint(list,tmpreg);
|
||||
end
|
||||
end
|
||||
if is_shifter_const(a,b) then
|
||||
list.concat(taicpu.op_reg_const(A_CMN,reg,a))
|
||||
{ CMN reg,0 and CMN reg,$80000000 are different from CMP reg,$ffffffff
|
||||
and CMP reg,$7fffffff regarding the flags according to the ARM manual }
|
||||
else if is_shifter_const(not(a),b) and (a<>$7fffffff) and (a<>$ffffffff) then
|
||||
list.concat(taicpu.op_reg_const(A_CMN,reg,not(a)))
|
||||
else
|
||||
internalerror(200308131);
|
||||
begin
|
||||
tmpreg:=rg.getregisterint(list,size);
|
||||
a_load_const_reg(list,size,a,tmpreg);
|
||||
list.concat(taicpu.op_reg_reg(A_CMP,reg,tmpreg));
|
||||
rg.ungetregisterint(list,tmpreg);
|
||||
end;
|
||||
a_jmp_cond(list,cmp_op,l);
|
||||
end;
|
||||
|
||||
@ -688,8 +673,8 @@ unit cgcpu;
|
||||
var
|
||||
ai : taicpu;
|
||||
begin
|
||||
ai := Taicpu.op_sym_cond(A_B,l,flags_to_cond(f));
|
||||
ai.is_jmp := true;
|
||||
ai:=setcondition(taicpu.op_sym(A_B,l),flags_to_cond(f));
|
||||
ai.is_jmp:=true;
|
||||
list.concat(ai);
|
||||
end;
|
||||
|
||||
@ -698,8 +683,8 @@ unit cgcpu;
|
||||
var
|
||||
ai : taicpu;
|
||||
begin
|
||||
list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f));
|
||||
list.concat(setcondition(aicpu.op_reg_const(A_MOV,reg,0),inverse_cond[flags_to_cond(f)]));
|
||||
list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f)));
|
||||
list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond[flags_to_cond(f)]));
|
||||
end;
|
||||
|
||||
|
||||
@ -733,7 +718,7 @@ unit cgcpu;
|
||||
procedure tcgarm.g_return_from_proc(list : taasmoutput;parasize : aword);
|
||||
begin
|
||||
if (current_procinfo.framepointer=NR_STACK_POINTER_REG) then
|
||||
list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14));
|
||||
list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14))
|
||||
else
|
||||
{ restore int registers and return }
|
||||
list.concat(setoppostfix(taicpu.op_reg_regset(A_LDM,NR_R11,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
|
||||
@ -753,25 +738,25 @@ unit cgcpu;
|
||||
begin
|
||||
tmpref:=ref;
|
||||
{ Be sure to have a base register }
|
||||
if (tmpref.base.number=NR_NO) then
|
||||
if (tmpref.base=NR_NO) then
|
||||
begin
|
||||
if tmpref.shiftmode<>SM_None then
|
||||
internalerror(200308294);
|
||||
tmpref.base:=tmpref.index;
|
||||
tmpref.index.number:=NR_NO;
|
||||
tmpref.index:=NR_NO;
|
||||
end;
|
||||
|
||||
if assigned(tmpref.symbol) or
|
||||
not(is_shifter_const(tmpref.offset,b)) or
|
||||
((tmpref.base.number<>NR_NO) and tmpref.index.number<>NR_NO)) then
|
||||
((tmpref.base<>NR_NO) and (tmpref.index<>NR_NO)) then
|
||||
fixref(list,tmpref);
|
||||
|
||||
if ref.index.number<>NR_NO then
|
||||
if ref.index<>NR_NO then
|
||||
begin
|
||||
end
|
||||
else
|
||||
{ else
|
||||
list.concat(taicpu.op_reg_reg(A_MOV,r,));
|
||||
ref.signindex<0 then
|
||||
ref.signindex<0 then }
|
||||
end;
|
||||
|
||||
|
||||
@ -807,13 +792,12 @@ unit cgcpu;
|
||||
tmpreg:=rg.getregisterint(list,OS_INT);
|
||||
reference_reset(tmpref);
|
||||
tmpref.symbol:=l;
|
||||
tmpref.base.enum:=R_INTREGISTER;
|
||||
tmpref.base.number:=NR_R15;
|
||||
tmpref.base:=NR_PC;
|
||||
list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
|
||||
|
||||
if (ref.base.number<>NR_NO) then
|
||||
if (ref.base<>NR_NO) then
|
||||
begin
|
||||
if ref.index.number<>NR_NO then
|
||||
if ref.index<>NR_NO then
|
||||
begin
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
|
||||
rg.ungetregister(list,ref.base);
|
||||
@ -953,13 +937,13 @@ unit cgcpu;
|
||||
end;
|
||||
|
||||
|
||||
procedure tcgarm.g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset);
|
||||
procedure tcgarm.g_save_standard_registers(list : taasmoutput; usedinproc : tsuperregisterset);
|
||||
begin
|
||||
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
|
||||
end;
|
||||
|
||||
|
||||
procedure tcgarm.g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset);
|
||||
procedure tcgarm.g_restore_standard_registers(list : taasmoutput; usedinproc : tsuperregisterset);
|
||||
begin
|
||||
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
|
||||
end;
|
||||
@ -1101,7 +1085,10 @@ begin
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.13 2003-09-04 00:15:29 florian
|
||||
Revision 1.14 2003-09-04 21:07:03 florian
|
||||
* ARM compiler compiles again
|
||||
|
||||
Revision 1.13 2003/09/04 00:15:29 florian
|
||||
* first bunch of adaptions of arm compiler for new register type
|
||||
|
||||
Revision 1.12 2003/09/03 19:10:30 florian
|
||||
|
||||
@ -116,6 +116,9 @@ unit cpubase;
|
||||
{ Available Registers }
|
||||
{$i rarmcon.inc}
|
||||
|
||||
{ aliases }
|
||||
NR_PC = NR_R15;
|
||||
|
||||
{ Integer Super registers first and last }
|
||||
{$warning Supreg shall be $00-$1f}
|
||||
first_int_supreg = RS_R3;
|
||||
@ -632,7 +635,10 @@ unit cpubase;
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.12 2003-09-04 00:15:29 florian
|
||||
Revision 1.13 2003-09-04 21:07:03 florian
|
||||
* ARM compiler compiles again
|
||||
|
||||
Revision 1.12 2003/09/04 00:15:29 florian
|
||||
* first bunch of adaptions of arm compiler for new register type
|
||||
|
||||
Revision 1.11 2003/09/03 19:10:30 florian
|
||||
|
||||
@ -108,8 +108,9 @@ interface
|
||||
R_INVALIDREGISTER, { = 0 }
|
||||
R_INTREGISTER, { = 1 }
|
||||
R_FPUREGISTER, { = 2 }
|
||||
{ used by Intel only }
|
||||
R_MMXREGISTER, { = 3 }
|
||||
R_KNIREGISTER, { = 4 }
|
||||
R_MMREGISTER, { = 4 }
|
||||
R_SPECIALREGISTER, { = 5 }
|
||||
R_ADDRESSREGISTER { = 6 }
|
||||
);
|
||||
@ -270,9 +271,9 @@ implementation
|
||||
R_FPUREGISTER:
|
||||
t:='f';
|
||||
R_MMXREGISTER:
|
||||
t:='x';
|
||||
R_MMREGISTER:
|
||||
t:='m';
|
||||
R_KNIREGISTER:
|
||||
t:='k';
|
||||
else
|
||||
begin
|
||||
result:='INVALID';
|
||||
@ -305,7 +306,10 @@ implementation
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.24 2003-09-03 21:06:19 peter
|
||||
Revision 1.25 2003-09-04 21:07:03 florian
|
||||
* ARM compiler compiles again
|
||||
|
||||
Revision 1.24 2003/09/03 21:06:19 peter
|
||||
* write INVALID as register name instead of IE
|
||||
|
||||
Revision 1.23 2003/09/03 16:29:37 peter
|
||||
|
||||
@ -107,7 +107,7 @@ M29,$03,$1d,M29,v29,M29,-1
|
||||
M30,$03,$1e,M30,v30,M30,-1
|
||||
M31,$03,$1f,M31,v31,M31,-1
|
||||
|
||||
CR,$05,$00,CR,cR,CR,-1
|
||||
CR,$05,$00,CR,cr,CR,-1
|
||||
CR0,$05,$01,CR0,cr0,CR0,68
|
||||
CR1,$05,$02,CR1,cr1,CR1,69
|
||||
CR2,$05,$03,CR2,cr2,CR2,70
|
||||
@ -123,7 +123,10 @@ FPSCR,$05,$0c,FPSCR,fpscr,FPSCR,-1
|
||||
|
||||
;
|
||||
; $Log$
|
||||
; Revision 1.3 2003-09-03 19:35:24 peter
|
||||
; Revision 1.4 2003-09-04 21:07:03 florian
|
||||
; * ARM compiler compiles again
|
||||
;
|
||||
; Revision 1.3 2003/09/03 19:35:24 peter
|
||||
; * powerpc compiles again
|
||||
;
|
||||
; Revision 1.2 2003/09/03 15:55:01 peter
|
||||
|
||||
@ -96,7 +96,7 @@
|
||||
'v29',
|
||||
'v30',
|
||||
'v31',
|
||||
'cR',
|
||||
'cr',
|
||||
'cr0',
|
||||
'cr1',
|
||||
'cr2',
|
||||
|
||||
@ -440,7 +440,7 @@ implementation
|
||||
R_FPUREGISTER :
|
||||
reg2opsize:=S_FL;
|
||||
R_MMXREGISTER,
|
||||
R_KNIREGISTER :
|
||||
R_MMREGISTER :
|
||||
reg2opsize:=S_D;
|
||||
R_SPECIALREGISTER :
|
||||
begin
|
||||
@ -563,7 +563,10 @@ implementation
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.15 2003-09-03 15:55:02 peter
|
||||
Revision 1.16 2003-09-04 21:07:03 florian
|
||||
* ARM compiler compiles again
|
||||
|
||||
Revision 1.15 2003/09/03 15:55:02 peter
|
||||
* NEWRA branch merged
|
||||
|
||||
Revision 1.14 2003/09/03 11:18:37 florian
|
||||
|
||||
Loading…
Reference in New Issue
Block a user