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* patch by Nico Erfurth:
Improve ARM-Peephole Optimizers
1.) Introduce a ARM-specific RegUsedAfterInstruction which analyzes
instructions and reg allocation information to see if a register is
really needed afterwards to decide if some special optimizations can be
done.
2.) Introduce "RemoveSuperfluousMove"
This tries to fold mov into a previous Data-Instruction (ADD, ORR, etc)
or LDR-Instruction.
3.) Introduce new Optimizer "DataMov2Data" and modify LdrMov2Ldr to use
RemoveSuperfluousMove
4.) Expand Ldr* and Str* Optimizers to also work on {Ldr,Str}{,b,h}
git-svn-id: trunk@21314 -
This commit is contained in:
florian
parent
ad4876dcb5
commit
05a8783b1e
@ -39,6 +39,9 @@ Type
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2;override;
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Function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
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procedure RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string);
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function RegUsedAfterInstruction(reg: Tregister; p: tai;
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var AllUsedRegs: TAllUsedRegs): Boolean;
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End;
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TCpuPreRegallocScheduler = class(TAsmOptimizer)
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@ -106,7 +109,7 @@ Implementation
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result := (oper.typ = top_reg) and (oper.reg = reg);
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end;
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procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList) ;
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procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList);
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begin
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if (taicpu(movp).condition = C_EQ) and
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(taicpu(cmpp).oper[0]^.reg = taicpu(movp).oper[0]^.reg) and
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@ -118,11 +121,91 @@ Implementation
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end;
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end;
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function regLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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begin
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p := taicpu(hp);
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regLoadedWithNewValue :=
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(assigned(hp)) and
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(hp.typ = ait_instruction) and
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(not(p.opcode in [A_STR, A_STRB, A_STRH, A_CMP, A_CMN, A_TST, A_TEQ,
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A_B, A_BL, A_BX, A_BLX])) and
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(p.oper[0]^.typ = top_reg) and
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(p.oper[0]^.reg = reg);
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end;
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function instructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
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var
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p: taicpu;
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i: longint;
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begin
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instructionLoadsFromReg := false;
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if not (assigned(hp) and (hp.typ = ait_instruction)) then
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exit;
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p:=taicpu(hp);
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i:=1;
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{For these instructions we have to start on oper[0]}
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if (p.opcode in [A_STR, A_STRB, A_STRH, A_CMP, A_CMN, A_TST, A_TEQ,
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A_B, A_BL, A_BX, A_BLX]) then i:=0;
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while(i<p.ops) do
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begin
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case p.oper[I]^.typ of
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top_reg:
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instructionLoadsFromReg := p.oper[I]^.reg = reg;
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top_regset:
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instructionLoadsFromReg := (getsupreg(reg) in p.oper[I]^.regset^);
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top_shifterop:
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instructionLoadsFromReg := p.oper[I]^.shifterop^.rs = reg;
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top_ref:
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instructionLoadsFromReg :=
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(p.oper[I]^.ref^.base = reg) or
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(p.oper[I]^.ref^.index = reg);
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end;
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if instructionLoadsFromReg then exit; {Bailout if we found something}
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Inc(I);
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end;
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end;
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function TCpuAsmOptimizer.RegUsedAfterInstruction(reg: Tregister; p: tai;
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var AllUsedRegs: TAllUsedRegs): Boolean;
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begin
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AllUsedRegs[getregtype(reg)].Update(tai(p.Next));
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RegUsedAfterInstruction :=
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(AllUsedRegs[getregtype(reg)].IsUsed(reg)) and
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(not(getNextInstruction(p,p)) or
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instructionLoadsFromReg(reg,p) or
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not(regLoadedWithNewValue(reg,p)));
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end;
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procedure TCpuAsmOptimizer.RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string);
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var
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TmpUsedRegs: TAllUsedRegs;
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begin
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if MatchInstruction(movp, A_MOV, [taicpu(p).condition], [PF_None]) and
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(taicpu(movp).ops=2) and {We can't optimize if there is a shiftop}
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MatchOperand(taicpu(movp).oper[1]^, taicpu(p).oper[0]^.reg) then
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begin
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CopyUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,movp,TmpUsedRegs)) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole '+optimizer+' removed superfluous mov')), movp);
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taicpu(p).loadreg(0,taicpu(movp).oper[0]^.reg);
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asml.remove(movp);
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movp.free;
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end;
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ReleaseUsedRegs(TmpUsedRegs);
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end;
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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hp1,hp2: tai;
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i: longint;
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TmpUsedRegs: TAllUsedRegs;
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begin
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result := false;
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case p.typ of
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@ -160,7 +243,9 @@ Implementation
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else
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*)
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case taicpu(p).opcode of
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A_STR:
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A_STR,
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A_STRH,
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A_STRB:
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begin
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{ change
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str reg1,ref
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@ -171,7 +256,17 @@ Implementation
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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(
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( (taicpu(p).opcode = A_STR) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None])
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) or
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( (taicpu(p).opcode = A_STRH) and
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MatchInstruction(hp1, A_LDRH, [taicpu(p).condition, C_None], [PF_None])
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) or
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( (taicpu(p).opcode = A_STRB) and
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MatchInstruction(hp1, A_LDRB, [taicpu(p).condition, C_None], [PF_None])
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)
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) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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begin
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@ -190,7 +285,11 @@ Implementation
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result := true;
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end;
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end;
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A_LDR:
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A_LDR,
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A_LDRH,
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A_LDRB,
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A_LDRSH,
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A_LDRSB:
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begin
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{ change
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ldr reg1,ref
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@ -201,7 +300,7 @@ Implementation
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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MatchInstruction(hp1, taicpu(p).opcode, [taicpu(p).condition, C_None], [PF_None]) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
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@ -221,8 +320,7 @@ Implementation
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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end;
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result := true;
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end
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else
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end;
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{ Remove superfluous mov after ldr
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changes
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ldr reg1, ref
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@ -236,22 +334,8 @@ Implementation
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* ldr+mov have the same conditions
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* mov does not set flags
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}
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if GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and
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(taicpu(hp1).ops=2) and {We can't optimize if there is a shiftop}
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) then
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begin
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CopyUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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If not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hp1,TmpUsedRegs)) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrMov2Ldr removed superfluous mov')), hp1);
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taicpu(p).loadreg(0,taicpu(hp1).oper[0]^.reg);
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asml.remove(hp1);
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hp1.free;
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end;
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ReleaseUsedRegs(TmpUsedRegs);
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end;
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if GetNextInstruction(p, hp1) then
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RemoveSuperfluousMove(p, hp1, 'LdrMov2Ldr');
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end;
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A_MOV:
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begin
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@ -311,7 +395,8 @@ Implementation
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(taicpu(p).oper[1]^.typ = top_const) and
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GetNextInstruction(p,hp1) then
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begin
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while MatchInstruction(hp1, A_STR, [], []) and
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while (tai(p).typ = ait_instruction) and
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(taicpu(p).opcode in [A_STR, A_STRH, A_STRB]) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) and
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GetNextInstruction(hp1, hp2) and
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MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [taicpu(p).oppostfix]) and
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@ -332,6 +417,8 @@ Implementation
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add r1, r1, #1
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to
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add r1, r0, #1
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Todo: Make it work for mov+cmp too
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}
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if (taicpu(p).ops = 2) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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@ -365,7 +452,16 @@ Implementation
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end;
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end;
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end;
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A_AND:
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A_ADD,
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A_ADC,
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A_RSB,
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A_RSC,
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A_SUB,
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A_SBC,
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A_AND,
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A_BIC,
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A_EOR,
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A_ORR:
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begin
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{
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change
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@ -374,7 +470,8 @@ Implementation
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to
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and reg2,reg1,(const1 and const2)
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}
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if (taicpu(p).oper[1]^.typ = top_reg) and
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if (taicpu(p).opcode = A_AND) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_AND, [taicpu(p).condition], [PF_None]) and
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@ -388,6 +485,15 @@ Implementation
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asml.remove(hp1);
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hp1.free;
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end;
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{
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change
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add reg1, ...
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mov reg2, reg1
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to
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add reg2, ...
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}
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if GetNextInstruction(p, hp1) then
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RemoveSuperfluousMove(p, hp1, 'DataMov2Data');
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end;
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A_CMP:
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begin
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