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* factored out PrePeepholeOptSxx
+ x86-64 uses PrePeepholeOptSxx now as well git-svn-id: trunk@36158 -
This commit is contained in:
florian
parent
9fc420b546
commit
06c4c651fd
@ -607,67 +607,9 @@ begin
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end;
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end;
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end;
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end;
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end;
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end;
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A_SAR, A_SHR:
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A_SAR,A_SHR:
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{changes the code sequence
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if PrePeepholeOptSxx(p) then
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shr/sar const1, x
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continue;
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shl const2, x
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to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
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begin
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if GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_SHL) and
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(taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(hp1).oper[0]^.typ = top_const) and
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(taicpu(hp1).opsize = taicpu(p).opsize) and
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(taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
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OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
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if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
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not(cs_opt_size in current_settings.optimizerswitches) then
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 > const2 }
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begin
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taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
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taicpu(hp1).opcode := A_AND;
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l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
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case taicpu(p).opsize Of
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S_L: taicpu(hp1).loadConst(0,l Xor aint($ffffffff));
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S_B: taicpu(hp1).loadConst(0,l Xor $ff);
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S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
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end;
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end
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else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
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not(cs_opt_size in current_settings.optimizerswitches) then
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 < const2 }
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begin
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taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
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taicpu(p).opcode := A_AND;
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l := (1 shl (taicpu(p).oper[0]^.val))-1;
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case taicpu(p).opsize Of
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S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
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S_B: taicpu(p).loadConst(0,l Xor $ff);
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S_W: taicpu(p).loadConst(0,l Xor $ffff);
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end;
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end
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else
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 = const2 }
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if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
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begin
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taicpu(p).opcode := A_AND;
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l := (1 shl (taicpu(p).oper[0]^.val))-1;
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case taicpu(p).opsize Of
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S_B: taicpu(p).loadConst(0,l Xor $ff);
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S_W: taicpu(p).loadConst(0,l Xor $ffff);
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S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
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end;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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A_XOR:
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A_XOR:
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if (taicpu(p).oper[0]^.typ = top_reg) and
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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@ -46,7 +46,14 @@ unit aoptx86;
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depend on the value in AH). }
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depend on the value in AH). }
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function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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procedure PostPeepholeOptMov(const p : tai);
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procedure DebugMsg(const s : string; p : tai);inline;
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procedure AllocRegBetween(reg : tregister; p1,p2 : tai;var initialusedregs : TAllUsedRegs);
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class function IsExitCode(p : tai) : boolean;
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class function isFoldableArithOp(hp1 : taicpu; reg : tregister) : boolean;
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procedure RemoveLastDeallocForFuncRes(p : tai);
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function PrePeepholeOptSxx(var p : tai) : boolean;
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function OptPass1AND(var p : tai) : boolean;
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function OptPass1AND(var p : tai) : boolean;
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function OptPass1VMOVAP(var p : tai) : boolean;
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function OptPass1VMOVAP(var p : tai) : boolean;
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@ -58,12 +65,7 @@ unit aoptx86;
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function OptPass2Jmp(var p : tai) : boolean;
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function OptPass2Jmp(var p : tai) : boolean;
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function OptPass2Jcc(var p : tai) : boolean;
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function OptPass2Jcc(var p : tai) : boolean;
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procedure DebugMsg(const s : string; p : tai);inline;
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procedure PostPeepholeOptMov(const p : tai);
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procedure AllocRegBetween(reg : tregister; p1,p2 : tai;var initialusedregs : TAllUsedRegs);
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class function IsExitCode(p : tai) : boolean;
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class function isFoldableArithOp(hp1 : taicpu; reg : tregister) : boolean;
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procedure RemoveLastDeallocForFuncRes(p : tai);
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end;
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end;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
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@ -284,6 +286,85 @@ unit aoptx86;
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end;
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end;
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function TX86AsmOptimizer.PrePeepholeOptSxx(var p : tai) : boolean;
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var
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hp1 : tai;
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l : TCGInt;
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begin
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result:=false;
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{ changes the code sequence
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shr/sar const1, x
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shl const2, x
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to
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either "sar/and", "shl/and" or just "and" depending on const1 and const2 }
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if GetNextInstruction(p, hp1) and
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MatchInstruction(hp1,A_SHL,[]) and
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(taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(hp1).oper[0]^.typ = top_const) and
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(taicpu(hp1).opsize = taicpu(p).opsize) and
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(taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
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OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
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begin
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if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
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not(cs_opt_size in current_settings.optimizerswitches) then
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begin
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 > const2 }
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taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
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taicpu(hp1).opcode := A_AND;
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l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
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case taicpu(p).opsize Of
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S_B: taicpu(hp1).loadConst(0,l Xor $ff);
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S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
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S_L: taicpu(hp1).loadConst(0,l Xor aint($ffffffff));
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S_Q: taicpu(hp1).loadConst(0,l Xor aint($ffffffffffffffff));
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else
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Internalerror(2017050703)
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end;
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end
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else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
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not(cs_opt_size in current_settings.optimizerswitches) then
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begin
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 < const2 }
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taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
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taicpu(p).opcode := A_AND;
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l := (1 shl (taicpu(p).oper[0]^.val))-1;
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case taicpu(p).opsize Of
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S_B: taicpu(p).loadConst(0,l Xor $ff);
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S_W: taicpu(p).loadConst(0,l Xor $ffff);
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S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
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S_Q: taicpu(p).loadConst(0,l Xor aint($ffffffffffffffff));
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else
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Internalerror(2017050702)
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end;
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end
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else if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
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begin
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{ shr/sar const1, %reg
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shl const2, %reg
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with const1 = const2 }
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taicpu(p).opcode := A_AND;
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l := (1 shl (taicpu(p).oper[0]^.val))-1;
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case taicpu(p).opsize Of
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S_B: taicpu(p).loadConst(0,l Xor $ff);
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S_W: taicpu(p).loadConst(0,l Xor $ffff);
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S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
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S_Q: taicpu(p).loadConst(0,l Xor aint($ffffffffffffffff));
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else
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Internalerror(2017050701)
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end;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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end;
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{ allocates register reg between (and including) instructions p1 and p2
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{ allocates register reg between (and including) instructions p1 and p2
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the type of p1 and p2 must not be in SkipInstr
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the type of p1 and p2 must not be in SkipInstr
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note that this routine is both called from the peephole optimizer
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note that this routine is both called from the peephole optimizer
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@ -31,6 +31,7 @@ uses cgbase, cpubase, aasmtai, aopt, aoptx86, aoptcpub;
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type
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type
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TCpuAsmOptimizer = class(TX86AsmOptimizer)
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TCpuAsmOptimizer = class(TX86AsmOptimizer)
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function PrePeepHoleOptsCpu(var p: tai): boolean; override;
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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function PeepHoleOptPass2Cpu(var p: tai): boolean; override;
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function PeepHoleOptPass2Cpu(var p: tai): boolean; override;
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function PostPeepHoleOptsCpu(var p : tai) : boolean; override;
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function PostPeepHoleOptsCpu(var p : tai) : boolean; override;
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@ -47,6 +48,20 @@ uses
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aasmbase, aasmdata, aasmcpu,
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aasmbase, aasmdata, aasmcpu,
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itcpugas;
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itcpugas;
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function TCpuAsmOptimizer.PrePeepHoleOptsCpu(var p : tai) : boolean;
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begin
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result := false;
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case p.typ of
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_SAR,A_SHR:
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result:=PrePeepholeOptSxx(p);
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end;
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end;
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end;
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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var
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hp1, hp2: tai;
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hp1, hp2: tai;
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