From 07b2982e7786325847fb8671706a59b8f07f5028 Mon Sep 17 00:00:00 2001
From: Jeppe Johansen <jeppe@j-software.dk>
Date: Sat, 1 Feb 2014 13:29:35 +0000
Subject: [PATCH] Don't do ARM FoldShiftLdrStr peephole optimization if there's
 an offset in the reference. Use UXTH+UXTB instructions instead of two shifts
 on processors that supports that. Eliminate internalerror when constant
 pointers are typecast as arrays.

git-svn-id: trunk@26647 -
---
 compiler/arm/aoptcpu.pas |  3 ++-
 compiler/arm/cgcpu.pas   | 10 +++++++++-
 compiler/ncgcnv.pas      |  4 ++++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/compiler/arm/aoptcpu.pas b/compiler/arm/aoptcpu.pas
index b0220f0b58..6539181bf8 100644
--- a/compiler/arm/aoptcpu.pas
+++ b/compiler/arm/aoptcpu.pas
@@ -1376,7 +1376,8 @@ Implementation
                            )
                          )
                        ) and
-                       { Only fold if there isn't another shifterop already. }
+                       { Only fold if there isn't another shifterop already, and offset is zero. }
+                       (taicpu(hp1).oper[1]^.ref^.offset = 0) and
                        (taicpu(hp1).oper[1]^.ref^.shiftmode = SM_None) and
                        not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) and
                        RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hp1)) then
diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas
index 26f7e12e5e..b27ee8ab31 100644
--- a/compiler/arm/cgcpu.pas
+++ b/compiler/arm/cgcpu.pas
@@ -1022,7 +1022,15 @@ unit cgcpu;
                     ((lsb = 0) or ((lsb + width) = 32)) then
               begin
                 shifterop_reset(so);
-                if lsb = 0 then
+                if (width = 16) and
+                   (lsb = 0) and
+                   (current_settings.cputype >= cpu_armv6) then
+                  list.concat(taicpu.op_reg_reg(A_UXTH,dst,src))
+                else if (width = 8) and
+                   (lsb = 0) and
+                   (current_settings.cputype >= cpu_armv6) then
+                  list.concat(taicpu.op_reg_reg(A_UXTB,dst,src))
+                else if lsb = 0 then
                   begin
                     so.shiftmode:=SM_LSL;
                     so.shiftimm:=32-width;
diff --git a/compiler/ncgcnv.pas b/compiler/ncgcnv.pas
index 471c618b98..42016b89c2 100644
--- a/compiler/ncgcnv.pas
+++ b/compiler/ncgcnv.pas
@@ -378,6 +378,10 @@ interface
               if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
                 location_freetemp(current_asmdata.CurrAsmList,left.location);
             end;
+          LOC_CONSTANT:
+            begin
+              location.reference.offset:=left.location.value;
+            end
           else
             internalerror(2002032216);
         end;