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+ patch by J. Gareth Moreton: SHL-centric peephole optimisations, resolves #37389
git-svn-id: trunk@45811 -
This commit is contained in:
florian
parent
d6d92e3666
commit
09125e834f
@ -3396,10 +3396,15 @@ unit aoptx86;
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TmpBool1,TmpBool2 : Boolean;
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TmpBool1,TmpBool2 : Boolean;
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tmpref : treference;
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tmpref : treference;
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hp1,hp2: tai;
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hp1,hp2: tai;
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mask: tcgint;
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begin
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begin
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Result:=false;
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Result:=false;
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if MatchOpType(taicpu(p),top_const,top_reg) and
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(taicpu(p).opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) and
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{ All these optimisations work on "shl/sal const,%reg" }
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if not MatchOpType(taicpu(p),top_const,top_reg) then
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Exit;
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if (taicpu(p).opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) and
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(taicpu(p).oper[0]^.val <= 3) then
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(taicpu(p).oper[0]^.val <= 3) then
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{ Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement }
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{ Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement }
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begin
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begin
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@ -3511,8 +3516,7 @@ unit aoptx86;
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end;
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end;
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end
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end
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{$ifndef x86_64}
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{$ifndef x86_64}
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else if (current_settings.optimizecputype < cpu_Pentium2) and
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else if (current_settings.optimizecputype < cpu_Pentium2) then
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MatchOpType(taicpu(p),top_const,top_reg) then
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begin
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begin
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{ changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
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{ changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
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but faster on a 486, and Tairable in both U and V pipes on the Pentium
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but faster on a 486, and Tairable in both U and V pipes on the Pentium
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@ -3540,7 +3544,130 @@ unit aoptx86;
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end;
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end;
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end
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end
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{$endif x86_64}
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{$endif x86_64}
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;
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else if
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GetNextInstruction(p, hp1) and (hp1.typ = ait_instruction) and MatchOpType(taicpu(hp1), top_const, top_reg) and
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(
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(
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MatchInstruction(hp1, A_AND, [taicpu(p).opsize]) and
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SetAndTest(hp1, hp2)
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{$ifdef x86_64}
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) or
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(
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MatchInstruction(hp1, A_MOV, [taicpu(p).opsize]) and
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GetNextInstruction(hp1, hp2) and
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MatchInstruction(hp2, A_AND, [taicpu(p).opsize]) and
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MatchOpType(taicpu(hp2), top_reg, top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(hp2).oper[0]^.reg)
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{$endif x86_64}
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)
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) and
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(taicpu(p).oper[1]^.reg = taicpu(hp2).oper[1]^.reg) then
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begin
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{ Change:
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shl x, %reg1
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mov -(1<<x), %reg2
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and %reg2, %reg1
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Or:
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shl x, %reg1
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and -(1<<x), %reg1
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To just:
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shl x, %reg1
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Since the and operation only zeroes bits that are already zero from the shl operation
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}
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case taicpu(p).oper[0]^.val of
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8:
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mask:=$FFFFFFFFFFFFFF00;
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16:
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mask:=$FFFFFFFFFFFF0000;
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32:
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mask:=$FFFFFFFF00000000;
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63:
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{ Constant pre-calculated to prevent overflow errors with Int64 }
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mask:=$8000000000000000;
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else
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begin
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if taicpu(p).oper[0]^.val >= 64 then
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{ Shouldn't happen realistically, since the register
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is guaranteed to be set to zero at this point }
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mask := 0
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else
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mask := -(Int64(1 shl taicpu(p).oper[0]^.val));
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end;
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end;
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if taicpu(hp1).oper[0]^.val = mask then
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begin
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{ Everything checks out, perform the optimisation, as long as
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the FLAGS register isn't being used}
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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{$ifdef x86_64}
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if (hp1 <> hp2) then
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begin
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{ "shl/mov/and" version }
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UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
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{ Don't do the optimisation if the FLAGS register is in use }
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if not(RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp2, TmpUsedRegs)) then
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begin
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DebugMsg(SPeepholeOptimization + 'ShlMovAnd2Shl', p);
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{ Don't remove the 'mov' instruction if its register is used elsewhere }
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if not(RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, hp2, TmpUsedRegs)) then
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begin
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asml.Remove(hp1);
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hp1.Free;
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Result := True;
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end;
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{ Only set Result to True if the 'mov' instruction was removed }
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asml.Remove(hp2);
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hp2.Free;
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end;
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end
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else
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{$endif x86_64}
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begin
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{ "shl/and" version }
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{ Don't do the optimisation if the FLAGS register is in use }
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if not(RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)) then
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begin
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DebugMsg(SPeepholeOptimization + 'ShlAnd2Shl', p);
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asml.Remove(hp1);
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hp1.Free;
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Result := True;
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end;
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end;
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Exit;
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end
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else {$ifdef x86_64}if (hp1 = hp2) then{$endif x86_64}
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begin
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{ Even if the mask doesn't allow for its removal, we might be
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able to optimise the mask for the "shl/and" version, which
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may permit other peephole optimisations }
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{$ifdef DEBUG_AOPTCPU}
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mask := taicpu(hp1).oper[0]^.val and mask;
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if taicpu(hp1).oper[0]^.val <> mask then
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begin
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DebugMsg(
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SPeepholeOptimization +
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'Changed mask from $' + debug_tostr(taicpu(hp1).oper[0]^.val) +
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' to $' + debug_tostr(mask) +
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'based on previous instruction (ShlAnd2ShlAnd)', hp1);
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taicpu(hp1).oper[0]^.val := mask;
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end;
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{$else DEBUG_AOPTCPU}
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{ If debugging is off, just set the operand even if it's the same }
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taicpu(hp1).oper[0]^.val := taicpu(hp1).oper[0]^.val and mask;
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{$endif DEBUG_AOPTCPU}
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end;
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end;
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end;
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end;
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@ -5357,6 +5484,35 @@ unit aoptx86;
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hp1.Free;
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hp1.Free;
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end;
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end;
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end
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end
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else if reg_and_hp1_is_instr and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(
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(taicpu(hp1).opcode = A_SHL) or (taicpu(hp1).opcode = A_SAL)
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) and
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(taicpu(hp1).oper[0]^.typ = top_const) and
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SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
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{ Minimum shift value allowed is the bit difference between the sizes }
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(taicpu(hp1).oper[0]^.val >=
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{ Multiply by 8 because tcgsize2size returns bytes, not bits }
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8 * (
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tcgsize2size[reg_cgsize(taicpu(p).oper[1]^.reg)] -
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tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)]
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)
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) then
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begin
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{ For:
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movsx/movzx %reg1,%reg1 (same register, just different sizes)
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shl/sal ##, %reg1
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Remove the movsx/movzx instruction if the shift overwrites the
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extended bits of the register (e.g. movslq %eax,%rax; shlq $32,%rax
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}
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DebugMsg(SPeepholeOptimization + 'MovxShl2Shl',p);
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RemoveCurrentP(p, hp1);
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Result := True;
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Exit;
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end
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else if taicpu(p).opcode=A_MOVZX then
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else if taicpu(p).opcode=A_MOVZX then
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begin
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begin
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{ removes superfluous And's after movzx's }
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{ removes superfluous And's after movzx's }
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