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* arm / a64: New optimisation for removing the number of necessary S/UXTB/H instructions
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
b1a9150160
commit
096d5f50b2
@ -60,6 +60,9 @@ Type
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function OptPass2Bitwise(var p: tai): Boolean;
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function OptPass2TST(var p: tai): Boolean;
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protected
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function DoXTArithOp(var p: tai; hp1: tai): Boolean;
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End;
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function MatchInstruction(const instr: tai; const op: TCommonAsmOps; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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@ -675,6 +678,123 @@ Implementation
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end;
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function TARMAsmOptimizer.DoXTArithOp(var p: tai; hp1: tai): Boolean;
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var
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hp2: tai;
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ConstLimit: TCGInt;
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ValidPostFixes: TOpPostFixes;
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FirstCode, SecondCode, ThirdCode, FourthCode: TAsmOp;
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begin
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Result := False;
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{ Change:
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uxtb/h reg1,reg1
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(operation on reg1 with immediate operand where the upper 24/56
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bits don't affect the state of the first 8 bits )
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uxtb/h reg1,reg1
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Remove first uxtb/h
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}
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case taicpu(p).opcode of
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A_UXTB,
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A_SXTB:
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begin
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ConstLimit := $FF;
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ValidPostFixes := [PF_B];
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FirstCode := A_UXTB;
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SecondCode := A_SXTB;
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ThirdCode := A_UXTB; { Used to indicate no other valid codes }
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FourthCode := A_SXTB;
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end;
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A_UXTH,
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A_SXTH:
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begin
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ConstLimit := $FFFF;
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ValidPostFixes := [PF_B, PF_H];
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FirstCode := A_UXTH;
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SecondCode := A_SXTH;
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ThirdCode := A_UXTB;
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FourthCode := A_SXTB;
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end;
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else
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InternalError(2024051401);
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end;
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{$ifndef AARCH64}
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{ Regular ARM doesn't have the multi-instruction MatchInstruction available }
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if (hp1.typ = ait_instruction) and (taicpu(hp1).oppostfix = PF_None) then
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case taicpu(hp1).opcode of
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A_ADD, A_SUB, A_MUL, A_LSL, A_AND, A_ORR, A_EOR, A_BIC, A_ORN:
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{$endif AARCH64}
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if
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(taicpu(p).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
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{$ifdef AARCH64}
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MatchInstruction(hp1, [A_ADD, A_SUB, A_MUL, A_LSL, A_AND, A_ORR, A_EOR, A_BIC, A_ORN, A_EON], [PF_None]) and
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{$endif AARCH64}
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(taicpu(hp1).condition = C_None) and
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(taicpu(hp1).ops = 3) and
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(taicpu(hp1).oper[0]^.reg = taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[2]^.typ = top_const) and
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(
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(
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{ If the AND immediate is 8-bit, then this essentially performs
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the functionality of the second UXTB and so its presence is
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not required }
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(taicpu(hp1).opcode = A_AND) and
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(taicpu(hp1).oper[2]^.val >= 0) and
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(taicpu(hp1).oper[2]^.val <= ConstLimit)
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) or
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(
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GetNextInstructionUsingReg(hp1,hp2,taicpu(p).oper[0]^.reg) and
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(hp2.typ = ait_instruction) and
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(taicpu(hp2).ops = 2) and
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(taicpu(hp2).condition = C_None) and
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(
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(
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(taicpu(hp2).opcode in [FirstCode, SecondCode, ThirdCode, FourthCode]) and
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(taicpu(hp2).oppostfix = PF_None) and
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(taicpu(hp2).oper[1]^.reg = taicpu(p).oper[0]^.reg)
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{ Destination is allowed to be different in this case, but
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only if the source is no longer in use (it being the same as
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the source is covered by RegEndOfLife as well) }
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) or
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(
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{ STRB essentially fills the same role as the second UXTB
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as long as the register is deallocated afterwards }
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MatchInstruction(hp2, A_STR, [C_None], ValidPostFixes) and
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(taicpu(hp2).oper[0]^.reg = taicpu(p).oper[0]^.reg) and
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not RegInOp(taicpu(p).oper[0]^.reg, taicpu(hp2).oper[1]^)
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)
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) and
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RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hp2))
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)
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) then
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begin
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DebugMsg(SPeepholeOptimization + 'S/Uxtb/hArithUxtb/h2ArithS/Uxtb/h done', p);
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Result := RemoveCurrentP(p);
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{ Simplify bitwise constants if able }
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{$ifdef AARCH64}
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if (taicpu(hp1).opcode in [A_AND, A_ORR, A_EOR, A_BIC, A_ORN, A_EON]) and
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is_shifter_const(taicpu(hp1).oper[2]^.val and ConstLimit, OS_32) then
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{$else AARCH64}
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if (
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(ConstLimit = $FF) or
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(taicpu(hp1).oper[2]^.val <= $100)
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) and
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(taicpu(hp1).opcode in [A_AND, A_ORR, A_EOR, A_BIC, A_ORN]) then
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{$endif AARCH64}
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taicpu(hp1).oper[2]^.val := taicpu(hp1).oper[2]^.val and ConstLimit;
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end;
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{$ifndef AARCH64}
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else
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;
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end;
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{$endif not AARCH64}
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end;
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function TARMAsmOptimizer.OptPass1UXTB(var p : tai) : Boolean;
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var
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hp1, hp2: tai;
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@ -773,6 +893,8 @@ Implementation
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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result:=RemoveCurrentP(p);
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end
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else if DoXTArithOp(p, hp1) then
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Result:=true
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{$ifdef AARCH64}
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else if USxtOp2Op(p,hp1,SM_UXTB) then
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Result:=true
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@ -862,6 +984,8 @@ Implementation
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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result:=RemoveCurrentP(p);
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end
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else if DoXTArithOp(p, hp1) then
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Result:=true
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{$ifdef AARCH64}
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else if USxtOp2Op(p,hp1,SM_UXTH) then
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Result:=true
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@ -974,6 +1098,8 @@ Implementation
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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result:=RemoveCurrentP(p);
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end
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else if DoXTArithOp(p, hp1) then
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Result:=true
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{$ifdef AARCH64}
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else if USxtOp2Op(p,hp1,SM_SXTB) then
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Result:=true
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@ -1094,6 +1220,8 @@ Implementation
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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result:=RemoveCurrentP(p);
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end
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else if DoXTArithOp(p, hp1) then
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Result:=true
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{$ifdef AARCH64}
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else if USxtOp2Op(p,hp1,SM_SXTH) then
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Result:=true
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