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+ aarch64 math nodes implementation
git-svn-id: trunk@29868 -
This commit is contained in:
Jonas Maebe
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@ -25,6 +25,7 @@ compiler/aarch64/itcpugas.pas svneol=native#text/plain
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compiler/aarch64/ncpuadd.pas svneol=native#text/plain
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compiler/aarch64/ncpucnv.pas svneol=native#text/plain
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compiler/aarch64/ncpuinl.pas svneol=native#text/plain
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compiler/aarch64/ncpumat.pas svneol=native#text/plain
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compiler/aarch64/ra64con.inc svneol=native#text/plain
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compiler/aarch64/ra64dwa.inc svneol=native#text/plain
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compiler/aarch64/ra64nor.inc svneol=native#text/plain
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187
compiler/aarch64/ncpumat.pas
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187
compiler/aarch64/ncpumat.pas
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@ -0,0 +1,187 @@
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{
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Copyright (c) 1998-2002, 2014 by Florian Klaempfl and Jonas Maebe
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Generate AArch64 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpumat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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taarch64moddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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end;
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taarch64notnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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taarch64unaryminusnode = class(tcgunaryminusnode)
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procedure second_float; override;
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end;
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implementation
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uses
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globtype,systems,constexp,
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cutils,verbose,globals,
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symconst,symdef,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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cgbase,cgobj,hlcgobj,pass_2,procinfo,
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ncon,
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cpubase,
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ncgutil,cgcpu,cgutils;
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{*****************************************************************************
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taarch64moddivnode
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*****************************************************************************}
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procedure taarch64moddivnode.pass_generate_code;
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var
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op : tasmop;
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tmpreg,
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numerator,
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divider,
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resultreg : tregister;
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hl : tasmlabel;
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overflowloc: tlocation;
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begin
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secondpass(left);
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secondpass(right);
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{ set result location }
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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resultreg:=location.register;
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{ put numerator in register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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numerator:=left.location.register;
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{ load divider in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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divider:=right.location.register;
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{ start division }
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if is_signed(left.resultdef) then
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op:=A_SDIV
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else
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op:=A_UDIV;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,numerator,divider));
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{ no divide-by-zero detection available in hardware, emulate (if it's a
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constant, this will have been detected earlier already) }
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if (right.nodetype<>ordconstn) then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,
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right.location.register,0));
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current_asmdata.getjumplabel(hl);
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current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_B,C_NE,hl));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO',false);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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{ in case of overflow checking, also check for low(int64) div (-1)
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(no hardware support for this either) }
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if (cs_check_overflow in current_settings.localswitches) and
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is_signed(left.resultdef) and
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((right.nodetype<>ordconstn) or
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(tordconstnode(right).value=-1)) then
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begin
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{ num=ffff... and div=8000... <=>
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num xor not(div xor 8000...) = 0
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(and we have the "eon" operation, which performs "xor not(...)" }
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
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hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,low(int64),left.location.register,tmpreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_EON,
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tmpreg,left.location.register,tmpreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,tmpreg,0));
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{ now the zero/equal flag is set in case we divided low(int64) by
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(-1) }
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location_reset(overflowloc,LOC_FLAGS,OS_NO);
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overflowloc.resflags:=F_EQ;
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cg.g_overflowcheck_loc(current_asmdata.CurrAsmList,location,resultdef,overflowloc);
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end;
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{ in case of modulo, multiply result again by the divider and subtract
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from the numerator }
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if nodetype=modn then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
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resultreg,divider,numerator));
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end;
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{*****************************************************************************
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taarch64notnode
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*****************************************************************************}
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procedure taarch64notnode.second_boolean;
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begin
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if not handle_locjump then
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER,
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LOC_REFERENCE, LOC_CREFERENCE,
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LOC_SUBSETREG, LOC_CSUBSETREG,
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LOC_SUBSETREF, LOC_CSUBSETREF:
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,
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left.location.register,0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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{*****************************************************************************
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taarch64unaryminusnode
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*****************************************************************************}
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procedure taarch64unaryminusnode.second_float;
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begin
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secondpass(left);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FNEG,location.register,left.location.register));
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end;
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begin
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cmoddivnode:=taarch64moddivnode;
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cnotnode:=taarch64notnode;
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cunaryminusnode:=taarch64unaryminusnode;
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end.
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