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+ more RiscV extensions

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* make use of F and D extension flags
This commit is contained in:
florian 2024-11-17 15:05:35 +01:00
parent 08762ab8f0
commit 0b49fba637
5 changed files with 49 additions and 16 deletions
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14
compiler/options.pas
View File

@ -5491,17 +5491,17 @@ begin
{ RISC-V defaults }
if (target_info.abi = abi_riscv_hf) then
begin
{$ifdef riscv32}
{$ifdef riscv32}
if not option.CPUSetExplicitly then
init_settings.cputype:=cpu_rv32ima;
init_settings.cputype:=cpu_rv32imafd;
if not option.OptCPUSetExplicitly then
init_settings.optimizecputype:=cpu_rv32ima;
{$else}
init_settings.optimizecputype:=cpu_rv32imafd;
{$else}
if not option.CPUSetExplicitly then
init_settings.cputype:=cpu_rv64imac;
init_settings.cputype:=cpu_rv64imafdc;
if not option.OptCPUSetExplicitly then
init_settings.optimizecputype:=cpu_rv64imac;
{$endif}
init_settings.optimizecputype:=cpu_rv64imafdc;
{$endif}
{ Set FPU type }
if not(option.FPUSetExplicitly) then

8
compiler/riscv/agrvgas.pas
View File

@ -233,12 +233,12 @@ unit agrvgas;
const
arch_str: array[boolean,tcputype] of string[10] = (
{$ifdef RISCV32}
('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32ec','rv32gc'),
('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32ecfd','rv32gc')
('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imafd','rv32ec','rv32gc'),
('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc')
{$endif RISCV32}
{$ifdef RISCV64}
('','rv64imac','rv64ima','rv64im','rv64i','rv64gc'),
('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64gc')
('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc'),
('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc')
{$endif RISCV64}
);
begin

3
compiler/riscv/cgrv.pas
View File

@ -1043,7 +1043,8 @@ unit cgrv;
ai: taicpu;
l: TAsmLabel;
begin
if needs_check_for_fpu_exceptions then
if (CPURV_HAS_F in cpu_capabilities[current_settings.cputype]) and
needs_check_for_fpu_exceptions then
begin
r:=getintregister(list,OS_INT);
list.concat(taicpu.op_reg(A_FRFLAGS,r));

20
compiler/riscv32/cpuinfo.pas
View File

@ -41,6 +41,8 @@ Type
cpu_rv32i,
cpu_rv32e,
cpu_rv32imc,
cpu_rv32imafdc,
cpu_rv32imafd,
cpu_rv32ec,
cpu_rv32gc
);
@ -173,6 +175,8 @@ Const
'RV32I',
'RV32E',
'RV32IMC',
'RV32IMAFDC',
'RV32IMAFD',
'RV32EC',
'RV32GC'
);
@ -210,7 +214,17 @@ Const
CPURV_HAS_ZBC,
CPURV_HAS_ZBS,
CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }
CPURV_HAS_FETCH_FENCE { extension Zifencei }
CPURV_HAS_FETCH_FENCE, { extension Zifencei }
CPURV_HAS_F,
CPURV_HAS_D,
CPURV_HAS_Q,
CPURV_HAS_ZFH,
CPURV_HAS_ZFHMIN,
CPURV_HAS_ZFA,
CPURV_HAS_ZFINX,
CPURV_HAS_ZDINX,
CPURV_HAS_ZHINX,
CPURV_HAS_ZHINXMIN
);
const
@ -222,8 +236,10 @@ Const
{ cpu_rv32i } [],
{ cpu_rv32e } [CPURV_HAS_16REGISTERS],
{ cpu_rv32imc } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
{ cpu_rv32imafdc} [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
{ cpu_rv32imafd } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
{ cpu_rv32ec } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT],
{ cpu_rv32gc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT]
{ cpu_rv32gc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D]
);
Implementation

20
compiler/riscv64/cpuinfo.pas
View File

@ -38,6 +38,8 @@ type
cpu_rv64ima,
cpu_rv64im,
cpu_rv64i,
cpu_rv64imafdc,
cpu_rv64imafd,
cpu_rv64gc
);
@ -92,6 +94,8 @@ Const
'RV64IMA',
'RV64IM',
'RV64I',
'RV64IMAFDC',
'RV64IMAFD',
'RV64GC'
);
@ -128,7 +132,17 @@ Const
CPURV_HAS_ZBC,
CPURV_HAS_ZBS,
CPURV_HAS_CSR_INSTRUCTIONS, { extension Zicsr }
CPURV_HAS_FETCH_FENCE { extension Zifencei }
CPURV_HAS_FETCH_FENCE, { extension Zifencei }
CPURV_HAS_F,
CPURV_HAS_D,
CPURV_HAS_Q,
CPURV_HAS_ZFH,
CPURV_HAS_ZFHMIN,
CPURV_HAS_ZFA,
CPURV_HAS_ZFINX,
CPURV_HAS_ZDINX,
CPURV_HAS_ZHINX,
CPURV_HAS_ZHINXMIN
);
const
@ -138,7 +152,9 @@ Const
{ cpu_rv64ima } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC],
{ cpu_rv64im } [CPURV_HAS_MUL],
{ cpu_rv64i } [],
{ cpu_rv64gc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_CSR_INSTRUCTIONS,CPURV_HAS_FETCH_FENCE]
{ cpu_rv64imafdc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
{ cpu_rv64imafd } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
{ cpu_rv64gc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_CSR_INSTRUCTIONS,CPURV_HAS_FETCH_FENCE,CPURV_HAS_F,CPURV_HAS_D]
);
implementation