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* Aarch64: set register size correctly for AndStrb2Strb optimization, resolves #37427

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git-svn-id: trunk@45872 -
This commit is contained in:
florian 2020-07-28 20:46:05 +00:00
parent cc936710a0
commit 0b5c50ea41
3 changed files with 20 additions and 0 deletions
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1
.gitattributes vendored
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@ -18390,6 +18390,7 @@ tests/webtbs/tw37397.pp svneol=native#text/plain
tests/webtbs/tw37398.pp svneol=native#text/pascal tests/webtbs/tw37398.pp svneol=native#text/pascal
tests/webtbs/tw37400.pp svneol=native#text/pascal tests/webtbs/tw37400.pp svneol=native#text/pascal
tests/webtbs/tw3742.pp svneol=native#text/plain tests/webtbs/tw3742.pp svneol=native#text/plain
tests/webtbs/tw37427.pp svneol=native#text/pascal
tests/webtbs/tw3751.pp svneol=native#text/plain tests/webtbs/tw3751.pp svneol=native#text/plain
tests/webtbs/tw3758.pp svneol=native#text/plain tests/webtbs/tw3758.pp svneol=native#text/plain
tests/webtbs/tw3764.pp svneol=native#text/plain tests/webtbs/tw3764.pp svneol=native#text/plain

4
compiler/armgen/aoptarm.pas
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@ -874,7 +874,11 @@ Implementation
not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
begin begin
DebugMsg('Peephole AndStrb2Strb done', p); DebugMsg('Peephole AndStrb2Strb done', p);
{$ifdef AARCH64}
taicpu(hp1).loadReg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[1]^.reg),R_SUBD));
{$else AARCH64}
taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg); taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
{$endif AARCH64}
AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,UsedRegs); AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,UsedRegs);
RemoveCurrentP(p); RemoveCurrentP(p);
result:=true; result:=true;

15
tests/webtbs/tw37427.pp Normal file
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@ -0,0 +1,15 @@
program ByteCompilerError;
{$Q+}
function NativeGetHashBytes: Byte;
var
LBitSize: Int64;
bob: byte;
begin
bob := LBitSize and $FF;
end;
begin
end.