mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-06 09:07:59 +02:00
* added workarounds for some load/store instructions requiring 4 byte aligned addresses
* some cleanup and optimization of 64 bit address loading in the code generator * small changes to the IDE to make it compile * stat type update for packages/cdrom compatibility git-svn-id: trunk@1375 -
This commit is contained in:
tom_at_work
parent
3a44a158ed
commit
0ba960e1bd
@ -125,7 +125,7 @@ type
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{ offset or symbol, in which case the base will have been changed }
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{ to a tempreg (which has to be freed by the caller) containing }
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{ the sum of part of the original reference }
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function fixref(list: taasmoutput; var ref: treference): boolean;
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function fixref(list: taasmoutput; var ref: treference; const size : TCgsize): boolean;
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{ returns whether a reference can be used immediately in a powerpc }
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{ instruction }
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@ -446,7 +446,7 @@ var
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ref2: TReference;
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begin
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2, tosize);
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if tosize in [OS_S8..OS_S64] then
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{ storing is the same for signed and unsigned values }
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tosize := tcgsize(ord(tosize) - (ord(OS_S8) - ord(OS_8)));
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@ -483,7 +483,7 @@ begin
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if not (fromsize in [OS_8, OS_S8, OS_16, OS_S16, OS_32, OS_S32, OS_64, OS_S64]) then
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internalerror(2002090902);
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2, tosize);
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{ the caller is expected to have adjusted the reference already }
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{ in this case }
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if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
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@ -491,9 +491,9 @@ begin
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op := loadinstr[fromsize, ref2.index <> NR_NO, false];
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// there is no LWAU instruction, simulate using ADDI and LWA
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if (op = A_LWAU) then begin
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list.concat(taicpu.op_reg_reg_const(A_ADDI, reg, reg, ref2.offset));
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ref2.offset := 0;
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op := A_LWA;
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list.concat(taicpu.op_reg_reg_const(A_ADDI, reg, reg, ref2.offset));
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ref2.offset := 0;
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op := A_LWA;
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end;
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a_load_store(list, op, reg, ref2);
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// sign extend shortint if necessary, since there is no
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@ -569,7 +569,7 @@ begin
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internalerror(200201121);
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end;
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2, size);
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op := fpuloadinstr[size, ref2.index <> NR_NO, false];
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a_load_store(list, op, reg, ref2);
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end;
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@ -590,7 +590,7 @@ begin
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if not (size in [OS_F32, OS_F64]) then
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internalerror(200201122);
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2, size);
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op := fpustoreinstr[size, ref2.index <> NR_NO, false];
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a_load_store(list, op, reg, ref2);
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end;
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@ -1200,7 +1200,7 @@ var
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begin
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ref2 := ref;
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fixref(list, ref2);
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fixref(list, ref2, OS_64);
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{ load a symbol }
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if assigned(ref2.symbol) or (ref2.offset < low(smallint)) or (ref2.offset > high(smallint)) then begin
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{ add the symbol's value to the base of the reference, and if the }
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@ -1518,75 +1518,134 @@ begin
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(ref.offset = 0)));
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end;
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function tcgppc.fixref(list: taasmoutput; var ref: treference): boolean;
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function tcgppc.fixref(list: taasmoutput; var ref: treference; const size : TCgsize): boolean;
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var
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tmpreg: tregister;
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needsAlign : boolean;
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begin
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result := false;
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if (ref.base = NR_NO) then
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begin
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needsAlign := size in [OS_S32, OS_64, OS_S64];
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if (ref.base = NR_NO) then begin
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ref.base := ref.index;
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ref.base := NR_NO;
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ref.index := NR_NO;
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end;
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if (ref.base <> NR_NO) then
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begin
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if (ref.index <> NR_NO) and
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((ref.offset <> 0) or assigned(ref.symbol)) then
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begin
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if (ref.base <> NR_NO) and (ref.index <> NR_NO) and
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((ref.offset <> 0) or assigned(ref.symbol)) then begin
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result := true;
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tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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list.concat(taicpu.op_reg_reg_reg(
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A_ADD, tmpreg, ref.base, ref.index));
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a_op_reg_reg_reg(list, OP_ADD, size, ref.base, ref.index, tmpreg);
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ref.index := NR_NO;
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ref.base := tmpreg;
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end
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end
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else if ref.index <> NR_NO then
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internalerror(200208102);
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end;
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end;
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procedure tcgppc.a_load_store(list: taasmoutput; op: tasmop; reg: tregister;
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ref: treference);
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var
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tmpreg: tregister;
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tmpreg, tmpreg2: tregister;
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tmpref: treference;
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largeOffset: Boolean;
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begin
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tmpreg := NR_NO;
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// at this point there must not be a combination of values in the ref treference
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// which is not possible to directly map to instructions of the PowerPC architecture
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if (ref.index <> NR_NO) and ((ref.offset <> 0) or (assigned(ref.symbol))) then
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internalerror(200310131);
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// for some instructions we need to check that the offset is divisible by at
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// least four. If not, add the bytes which are "off" to the base register and
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// adjust the offset accordingly
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case op of
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A_LD, A_LDU, A_STD, A_STDU, A_LWA, A_LWAU :
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if ((ref.offset mod 4) <> 0) then begin
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tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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if (ref.base <> NR_NO) then begin
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a_op_const_reg_reg(list, OP_ADD, OS_ADDR, ref.offset mod 4, ref.base, tmpreg);
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ref.base := tmpreg;
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end else begin
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list.concat(taicpu.op_reg_const(A_LI, tmpreg, ref.offset mod 4));
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ref.base := tmpreg;
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end;
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ref.offset := (ref.offset div 4) * 4;
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end;
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end;
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// if we have to load/store from a symbol or large addresses, use a temporary register
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// containing the address
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if assigned(ref.symbol) or (ref.offset < low(smallint)) or (ref.offset > high(smallint)) then begin
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tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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if assigned(ref.symbol) or (ref.offset < low(smallint)) or (ref.offset > high(smallint)) then begin
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tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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reference_reset(tmpref);
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tmpref.symbol := ref.symbol;
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tmpref.relsymbol := ref.relsymbol;
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tmpref.offset := ref.offset;
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if (ref.base <> NR_NO) then begin
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{
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As long as the TOC isn't working we try to achieve highest speed (in this
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case by allowing instructions execute in parallel) as possible, at the cost
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of using another temporary register. So the code template when there is
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a base register and an offset is the following:
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lis rT1, SYM+offs@highest
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ori rT1, rT1, SYM+offs@higher
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lis rT2, SYM+offs@high
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ori rT2, SYM+offs@low
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rldimi rT2, rT1, 32
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<op>X reg, base, rT2
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}
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tmpreg2 := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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tmpref.refaddr := addr_highest;
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list.concat(taicpu.op_reg_ref(A_LIS, tmpreg, tmpref));
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tmpref.refaddr := addr_higher;
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list.concat(taicpu.op_reg_reg_ref(A_ORI, tmpreg, tmpreg, tmpref));
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tmpref.refaddr := addr_high;
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list.concat(taicpu.op_reg_ref(A_LIS, tmpreg2, tmpref));
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tmpref.refaddr := addr_low;
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list.concat(taicpu.op_reg_reg_ref(A_ORI, tmpreg2, tmpreg2, tmpref));
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list.concat(taicpu.op_reg_reg_const_const(A_RLDIMI, tmpreg2, tmpreg, 32, 0));
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reference_reset(tmpref);
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tmpref.symbol := ref.symbol;
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tmpref.relsymbol := ref.relsymbol;
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tmpref.offset := ref.offset;
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tmpref.base := ref.base;
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tmpref.index := tmpreg2;
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case op of
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// the code generator doesn't generate update instructions anyway
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A_LBZ : op := A_LBZX;
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A_LHZ : op := A_LHZX;
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A_LWZ : op := A_LWZX;
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A_LD : op := A_LDX;
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A_LHA : op := A_LHAX;
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A_LWA : op := A_LWAX;
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A_LFS : op := A_LFSX;
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A_LFD : op := A_LFDX;
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(*
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code template when there's no base register
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A_STB : op := A_STBX;
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A_STH : op := A_STHX;
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A_STW : op := A_STWX;
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A_STD : op := A_STDX;
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lis rT,SYM+offs@highesta
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addi rT,SYM+offs@highera
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sldi rT,rT,32
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addis rT,rT,SYM+offs@ha
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ld rD,SYM+offs@l(rT)
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code template when there's a base register
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lis rT,SYM+offs@highesta
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addis rT,SYM+offs@highera
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sldi rT,rT,32
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addis rT,rT,SYM+offs@ha
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add rT,rBase,rT
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ld rD,SYM+offs@l(rT)
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*)
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//list.concat(tai_comment.create(strpnew('symbol: ' + tmpref.symbol.name + ' offset: ' + inttostr(tmpref.offset))));
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A_STFS : op := A_STFSX;
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A_STFD : op := A_STFDX;
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else
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// unknown load/store opcode
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internalerror(2005101302);
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end;
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list.concat(taicpu.op_reg_ref(op, reg, tmpref));
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end else begin
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{ when accessing value from a reference without a base register, use the
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following code template:
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lis rT,SYM+offs@highesta
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ori rT,SYM+offs@highera
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sldi rT,rT,32
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oris rT,rT,SYM+offs@ha
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ld rD,SYM+offs@l(rT)
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}
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tmpref.refaddr := addr_highesta;
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list.concat(taicpu.op_reg_ref(A_LIS, tmpreg, tmpref));
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tmpref.refaddr := addr_highera;
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@ -1595,16 +1654,13 @@ begin
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tmpref.refaddr := addr_higha;
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list.concat(taicpu.op_reg_reg_ref(A_ORIS, tmpreg, tmpreg, tmpref));
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if (ref.base <> NR_NO) then begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD, tmpreg, tmpreg, ref.base));
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end;
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tmpref.base := tmpreg;
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tmpref.refaddr := addr_low;
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list.concat(taicpu.op_reg_ref(op, reg, tmpref));
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end else begin
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list.concat(taicpu.op_reg_ref(op, reg, ref));
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end;
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end else begin
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list.concat(taicpu.op_reg_ref(op, reg, ref));
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end;
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end;
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procedure tcgppc.a_jmp(list: taasmoutput; op: tasmop; c: tasmcondflag;
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@ -867,6 +867,7 @@ begin
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GetAsmReservedWordCount:=ord(lastop) - ord(firstop)
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{$ifndef x86_64}
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{$ifndef powerpc}
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{$ifndef powerpc64}
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{$ifndef arm}
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+ CondAsmOps*(ord(high(TasmCond))-ord(low(TasmCond)));
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{$else arm}
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@ -874,6 +875,9 @@ begin
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we've to solve this different }
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;
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{$endif arm}
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{$else powerpc64}
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+ CondAsmOps*(ord(high(TAsmCondFlag))-ord(low(TAsmCondFlag)));
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{$endif powerpc64}
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{$else powerpc}
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+ CondAsmOps*(ord(high(TAsmCondFlag))-ord(low(TAsmCondFlag)));
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{$endif powerpc}
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@ -13,24 +13,47 @@
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**********************************************************************}
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Stat = packed record // No unix typing because of differences
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st_dev : qword;
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st_ino : qword;
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st_nlink : qword;
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case integer of
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0 : (
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st_dev : qword;
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st_ino : qword;
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st_nlink : qword;
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st_mode : dword;
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st_uid : dword;
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st_gid : dword;
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__pad0 : dword;
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st_rdev : qword;
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st_size : int64;
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st_blksize : int64;
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st_blocks : int64; { Number 512-byte blocks allocated. }
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st_mode : dword;
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st_uid : dword;
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st_gid : dword;
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__pad0 : dword;
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st_rdev : qword;
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st_size : int64;
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st_blksize : int64;
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st_blocks : int64; { Number 512-byte blocks allocated. }
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st_atime : qword;
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__reserved0 : qword; { reserved for atime.nanoseconds }
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st_mtime : qword;
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__reserved1 : qword; { reserved for atime.nanoseconds }
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st_ctime : qword;
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__reserved2 : qword; { reserved for atime.nanoseconds }
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__unused : array[0..2] of int64;
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st_atime : qword;
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__reserved0 : qword; { reserved for atime.nanoseconds }
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st_mtime : qword;
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__reserved1 : qword; { reserved for atime.nanoseconds }
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st_ctime : qword;
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__reserved2 : qword; { reserved for atime.nanoseconds }
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__unused : array[0..2] of int64
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);
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1 : (
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dev : qword;
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ino,
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mode : qword;
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nlink_dummy : dword;
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uid_dummy,
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gid_dummy,
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rdev : dword;
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size : qword;
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blksize,
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blocks,
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atime,
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__unused1_dummy,
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mtime,
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__unused2_dummy,
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ctime,
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__unused3_dummy,
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__unused4_dummy,
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__unused5_dummy : qword;
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);
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end;
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@ -42,7 +42,7 @@ function setjmp(var S : jmp_buf) : longint;assembler;[Public, alias : 'FPC_SETJM
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mfcr r0
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std r16,40(r3) // store r16
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stfd f16,192(r3) // store f16
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std r0,168(r3) // store cr
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stw r0,168(r3) // store cr
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std r17,48(r3) // store r17
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stfd f17,200(r3) // store f17
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std r18,56(r3) // ...
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@ -100,7 +100,7 @@ procedure longjmp(var S : jmp_buf;value : longint);assembler;[Public, alias : 'F
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lfd f21,232(r3)
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ld r22,88(r3)
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lfd f22,240(r3)
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ld r0,168(r3)
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lwz r0,168(r3)
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ld r23,96(r3)
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lfd f23,248(r3)
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ld r24,104(r3)
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