paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-11-04 15:39:24 +01:00
Code Issues Packages Projects Releases Wiki Activity

+ support to use r0 for ppc/ppc64 when compiling the compiler with

Browse Source 
-duser0. Not active by default because generates wrong code due
    to bug in the register allocator

git-svn-id: trunk@7261 -
This commit is contained in:
Jonas Maebe 2007-05-04 14:52:05 +00:00
parent 63f80f3472
commit 0caee5b45b
4 changed files with 77 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
compiler/powerpc/cgcpu.pas
View File

@ -157,16 +157,16 @@ const
RS_R14,RS_R13],first_int_imreg,[]);
end
else}
rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
[RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
[{$ifdef user0} RS_R0,{$endif} RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
RS_R14,RS_R13],first_int_imreg,[]);
end
else
rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
[RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
[{$ifdef user0} RS_R0,{$endif}RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
@ -1172,8 +1172,10 @@ const
abi_powerpc_sysv:
reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_SYSV);
end;
a_reg_alloc(list,NR_R0);
list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
list.concat(taicpu.op_reg(A_MTLR,NR_R0));
a_reg_dealloc(list,NR_R0);
end;
(*

8
compiler/powerpc64/cgcpu.pas
View File

@ -395,16 +395,16 @@ procedure tcgppc.init_register_allocators;
begin
inherited init_register_allocators;
if (target_info.system <> system_powerpc64_darwin) then
rg[R_INTREGISTER] := trgcpu.create(R_INTREGISTER, R_SUBWHOLE,
[RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
rg[R_INTREGISTER] := trgintcpu.create(R_INTREGISTER, R_SUBWHOLE,
[{$ifdef user0} RS_R0, {$endif} RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,
RS_R14, RS_R13], first_int_imreg, [])
else
{ special for darwin/ppc64: r2 available volatile, r13 = tls }
rg[R_INTREGISTER] := trgcpu.create(R_INTREGISTER, R_SUBWHOLE,
[RS_R2, RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
rg[R_INTREGISTER] := trgintcpu.create(R_INTREGISTER, R_SUBWHOLE,
[{$ifdef user0} RS_R0, {$endif} RS_R2, RS_R3, RS_R4, RS_R5, RS_R6, RS_R7, RS_R8,
RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,

2
compiler/ppcgen/aasmcpu.pas
View File

@ -396,7 +396,7 @@ uses cutils, cclasses;
A_STW, A_STWX,
A_STFS, A_STFSX, A_STFD, A_STFDX, A_STFIWX, A_STHBRX, A_STWBRX, A_STWCX_,
A_CMP, A_CMPI, A_CMPL, A_CMPLI,
A_DCBA, A_DCBI, A_DCBST, A_DCBT, A_DCBTST, A_DCBZ,
A_DCBA, A_DCBI, A_DCBST, A_DCBT, A_DCBTST, A_DCBZ, A_DCBF, A_ICBI,
A_ECOWX, A_FCMPO, A_FCMPU, A_MTMSR, A_TLBIE, A_TW, A_TWI,
A_CMPWI, A_CMPW, A_CMPLWI, A_CMPLW, A_MT, A_MTLR, A_MTCTR
{$ifdef cpu64bit}

68
compiler/ppcgen/rgcpu.pas
View File

@ -39,6 +39,12 @@ unit rgcpu;
procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
end;
trgintcpu = class(trgcpu)
{$ifdef user0}
procedure add_cpu_interferences(p : tai);override;
{$endif user0}
end;
implementation
uses
@ -63,7 +69,10 @@ unit rgcpu;
internalerror(200704201);
if getregtype(tempreg)=R_INTREGISTER then
hreg:=getregisterinline(helplist,R_SUBWHOLE)
begin
hreg:=getregisterinline(helplist,R_SUBWHOLE);
add_edge(getsupreg(hreg),RS_R0);
end
else
hreg:=cg.getintregister(helplist,OS_ADDR);
reference_reset(tmpref);
@ -102,7 +111,10 @@ unit rgcpu;
internalerror(200704201);
if getregtype(tempreg)=R_INTREGISTER then
hreg:=getregisterinline(helplist,R_SUBWHOLE)
begin
hreg:=getregisterinline(helplist,R_SUBWHOLE);
add_edge(getsupreg(hreg),RS_R0);
end
else
hreg:=cg.getintregister(helplist,OS_ADDR);
reference_reset(tmpref);
@ -124,4 +136,56 @@ unit rgcpu;
inherited do_spill_written(list,pos,spilltemp,tempreg);
end;
{$ifdef user0}
procedure trgintcpu.add_cpu_interferences(p : tai);
var
r : tregister;
begin
if p.typ=ait_instruction then
begin
case taicpu(p).opcode of
A_ADDI, A_ADDIS,
A_STB, A_LBZ, A_STBX, A_LBZX, A_STH, A_LHZ, A_STHX, A_LHZX, A_LHA, A_LHAX,
A_STBU, A_LBZU, A_STBUX, A_LBZUX, A_STHU, A_LHZU, A_STHUX, A_LHZUX, A_LHAUX,
A_STW, A_LWZ, A_STWX, A_LWZX,
A_STWU, A_LWZU, A_STWUX, A_LWZUX,
A_STFS, A_LFS, A_STFSX, A_LFSX, A_STFD, A_LFD, A_STFDX, A_LFDX, A_STFIWX,
A_STFSU, A_LFSU, A_STFSUX, A_LFSUX, A_STFDU, A_LFDU, A_STFDUX, A_LFDUX,
A_STHBRX, A_LHBRX, A_STWBRX, A_LWBRX, A_STWCX_, A_LWARX,
A_ECIWX, A_ECOWX,
A_LMW, A_STMW,A_LSWI,A_LSWX,A_STSWI,A_STSWX
{$ifdef cpu64bit}
, A_STDU, A_STDUX,
A_LDU, A_LDUX,
A_STD, A_STDX,
A_LD, A_LDX,
A_LWA, A_LWAX, A_LWAUX,
A_STDCX_,A_LDARX
{$endif cpu64bit}
:
begin
case taicpu(p).oper[1]^.typ of
top_reg:
add_edge(getsupreg(taicpu(p).oper[1]^.reg),RS_R0);
top_ref:
if (taicpu(p).oper[1]^.ref^.base <> NR_NO) then
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),RS_R0);
end;
end;
A_DCBA, A_DCBI, A_DCBST, A_DCBT, A_DCBTST, A_DCBZ, A_DCBF, A_ICBI:
begin
case taicpu(p).oper[0]^.typ of
top_reg:
add_edge(getsupreg(taicpu(p).oper[0]^.reg),RS_R0);
top_ref:
if (taicpu(p).oper[0]^.ref^.base <> NR_NO) then
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),RS_R0);
end;
end;
end;
end;
end;
{$endif user0}
end.