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+ IsSimpleRef() function that can be used to determine whether a reference
is a valid AArch64 memory reference or not. It returns an enum that says
it's either valid, invalid, or invalid in a way that should trigger an
internal error in case we created the reference ourselves (as opposed to
it coming in via the assembler reader)
git-svn-id: trunk@29846 -
This commit is contained in:
Jonas Maebe
parent
84cea76f7a
commit
0ce5a1de7f
@ -222,6 +222,21 @@ uses
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{ nothing to add }
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end;
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type
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tsimplereftype =
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{ valid reference }
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(sr_simple,
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{ invalid reference, should not be generated by the code generator (but
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can be encountered via inline assembly, where it must be rejected) }
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sr_internal_illegal,
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{ invalid reference, may be generated by the code generator and then
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must be simplified (also rejected in inline assembly) }
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sr_complex);
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function simple_ref_type(op: tasmop; size:tcgsize; oppostfix: toppostfix; const ref: treference): tsimplereftype;
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function can_be_shifter_operand(opc: tasmop; opnr: longint): boolean;
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function valid_shifter_operand(opc: tasmop; useszr, usessp, is64bit: boolean; sm: tshiftmode; shiftimm: longint): boolean;
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function spilling_create_load(const ref: treference; r: tregister): taicpu;
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function spilling_create_store(r: tregister; const ref: treference): taicpu;
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@ -500,6 +515,277 @@ implementation
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end;
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function is_valid_load_symbol(op: tasmop; oppostfix: toppostfix; const ref: treference): tsimplereftype;
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begin
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result:=sr_complex;
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if not assigned(ref.symboldata) and
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not(ref.refaddr in [addr_pic,addr_gotpageoffset,addr_gotpage]) then
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exit;
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{ can't use pre-/post-indexed mode here (makes no sense either) }
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if ref.addressmode<>AM_OFFSET then
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exit;
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{ "ldr literal" must be a 32/64 bit LDR and have a symbol }
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if assigned(ref.symboldata) and
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((op<>A_LDR) or
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not(oppostfix in [PF_NONE,PF_W,PF_SW]) or
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not assigned(ref.symbol)) then
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exit;
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{ if this is a got offset load, we must have a base register and a
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symbol }
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if (ref.refaddr=addr_gotpageoffset) and
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(not assigned(ref.symbol) or
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(ref.base=NR_NO) or
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(ref.index<>NR_NO) or
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(ref.offset<>0)) then
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begin
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result:=sr_internal_illegal;
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exit;
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end;
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{ cannot have base or index register (we generate these kind of
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references internally, they should never end up here with an
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extra base or offset) }
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if (ref.refaddr in [addr_gotpage,addr_pic]) and
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(ref.base<>NR_NO) or
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(ref.index<>NR_NO) then
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begin
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result:=sr_internal_illegal;
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exit;
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end;
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result:=sr_simple;
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end;
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function simple_ref_type(op: tasmop; size:tcgsize; oppostfix: toppostfix; const ref: treference): tsimplereftype;
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var
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maxoffs: asizeint;
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accesssize: longint;
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begin
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result:=sr_internal_illegal;
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{ post-indexed is only allowed for vector and immediate loads/stores }
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if (ref.addressmode=AM_POSTINDEXED) and
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not(op in [A_LD1,A_LD2,A_LD3,A_LD4,A_ST1,A_ST2,A_ST3,A_ST4]) and
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(not(op in [A_LDR,A_STR,A_LDP,A_STP]) or
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(ref.base=NR_NO) or
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(ref.index<>NR_NO)) then
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exit;
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{ can only have a shift mode if we have an index }
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if (ref.index=NR_NO) and
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(ref.shiftmode<>SM_None) then
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exit;
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{ the index can never be the stack pointer }
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if ref.index=NR_SP then
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exit;
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{ no instruction supports an index without a base }
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if (ref.base=NR_NO) and
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(ref.index<>NR_NO) then
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begin
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result:=sr_complex;
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exit;
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end;
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{ LDR literal or GOT entry: 32 or 64 bit, label }
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if assigned(ref.symboldata) or
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assigned(ref.symbol) then
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begin
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{ we generate these kind of references internally; at least for now,
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they should never end up here with an extra base or offset or so }
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result:=is_valid_load_symbol(op,oppostfix,ref);
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exit;
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end;
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{ any other reference cannot be gotpage/gotpageoffset/pic }
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if ref.refaddr in [addr_gotpage,addr_gotpageoffset,addr_pic] then
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exit;
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{ base & index:
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* index cannot be the stack pointer
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* offset must be 0
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* can scale with the size of the access
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* can zero/sign extend 32 bit index register, and/or multiple by
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access size
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* no pre/post-indexing
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}
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if (ref.base<>NR_NO) and
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(ref.index<>NR_NO) then
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begin
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if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
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exit;
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case op of
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{ this holds for both integer and fpu/vector loads }
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A_LDR,A_STR:
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if (ref.offset=0) and
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(((ref.shiftmode=SM_None) and
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(ref.shiftimm=0)) or
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((ref.shiftmode in [SM_LSL,SM_UXTW,SM_SXTW]) and
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(ref.shiftimm=tcgsizep2size[size]))) then
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result:=sr_simple
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else
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result:=sr_complex;
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{ todo }
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A_LD1,A_LD2,A_LD3,A_LD4,
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A_ST1,A_ST2,A_ST3,A_ST4:
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internalerror(2014110704);
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{ these don't support base+index }
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A_LDUR,A_STUR,
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A_LDP,A_STP:
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result:=sr_complex;
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else
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{ nothing: result is already sr_internal_illegal };
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end;
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exit;
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end;
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{ base + immediate offset. Variants:
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* LDR*/STR*:
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- pre- or post-indexed with signed 9 bit immediate
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- regular with unsiged scaled immediate (multiple of access
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size), in the range 0 to (12 bit * access_size)-1
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* LDP/STP
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- pre- or post-indexed with signed 9 bit immediate
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- regular with signed 9 bit immediate
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* LDUR*/STUR*:
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- regular with signed 9 bit immediate
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}
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if ref.base<>NR_NO then
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begin
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accesssize:=1 shl tcgsizep2size[size];
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case op of
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A_LDR,A_STR:
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begin
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if (ref.addressmode=AM_OFFSET) and
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(ref.offset>=0) and
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(ref.offset<(((1 shl 12)-1)*accesssize)) and
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((ref.offset mod accesssize)=0) then
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result:=sr_simple
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else if (ref.offset>=-256) and
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(ref.offset<=255) then
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begin
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{ non pre-/post-indexed regular loads/stores can only be
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performed using LDUR/STUR }
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if ref.addressmode in [AM_PREINDEXED,AM_POSTINDEXED] then
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result:=sr_simple
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else
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result:=sr_complex
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end
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else
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result:=sr_complex;
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end;
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A_LDP,A_STP:
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begin
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{ only supported for 32/64 bit }
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if not(oppostfix in [PF_W,PF_SW,PF_None]) then
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exit;
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{ offset must be a multple of the access size }
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if (ref.offset mod accesssize)<>0 then
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exit;
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{ offset must fit in a signed 7 bit offset }
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if (ref.offset>=-(1 shl (6+tcgsizep2size[size]))) and
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(ref.offset<=(1 shl (6+tcgsizep2size[size]))-1) then
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result:=sr_simple
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else
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result:=sr_complex;
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end;
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A_LDUR,A_STUR:
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begin
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if (ref.addressmode=AM_OFFSET) and
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(ref.offset>=-256) and
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(ref.offset<=255) then
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result:=sr_simple
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else
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result:=sr_complex;
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end;
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{ todo }
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A_LD1,A_LD2,A_LD3,A_LD4,
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A_ST1,A_ST2,A_ST3,A_ST4:
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internalerror(2014110907);
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else
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{ nothing: result is already sr_internal_illegal };
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end;
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exit;
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end;
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{ absolute addresses are not supported, have to load them first into
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a register }
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result:=sr_complex;
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end;
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function can_be_shifter_operand(opc: tasmop; opnr: longint): boolean;
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begin
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case opc of
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A_ADD,
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A_AND,
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A_EON,
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A_EOR,
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A_ORN,
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A_ORR,
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A_SUB:
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result:=opnr=3;
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A_BIC,
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A_CMN,
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A_CMP,
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A_MOVK,
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A_MOVZ,
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A_MOVN,
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A_MVN,
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A_NEG,
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A_TST:
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result:=opnr=2;
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else
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result:=false;
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end;
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end;
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function valid_shifter_operand(opc: tasmop; useszr, usessp, is64bit: boolean; sm: tshiftmode; shiftimm: longint): boolean;
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begin
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case opc of
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A_ADD,
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A_SUB,
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A_NEG,
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A_AND,
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A_TST,
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A_CMN,
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A_CMP:
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begin
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result:=false;
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if not useszr then
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result:=
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(sm in shiftedregmodes) and
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((shiftimm in [0..31]) or
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(is64bit and
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(shiftimm in [32..63])));
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if not usessp then
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result:=
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result or
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((sm in extendedregmodes) and
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(shiftimm in [0..4]));
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end;
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A_BIC,
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A_EON,
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A_EOR,
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A_MVN,
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A_ORN,
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A_ORR:
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result:=
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(sm in shiftedregmodes) and
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(shiftimm in [0..31*(ord(is64bit)+1)+ord(is64bit)]);
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A_MOVK,
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A_MOVZ,
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A_MOVN:
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result:=
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(sm=SM_LSL) and
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((shiftimm in [0,16]) or
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(is64bit and
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(shiftimm in [32,48])));
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else
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result:=false;
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end;
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end;
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function spilling_create_load(const ref: treference; r: tregister): taicpu;
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var
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op: tasmop;
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