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* i386: make use of *fence instructions
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@ -1498,9 +1498,12 @@ end;
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procedure ReadBarrier;assembler;nostackframe;
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asm
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{$ifdef CPUX86_HAS_SSE2}
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lfence
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{$else CPUX86_HAS_SSE2}
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lock
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addl $0,0(%esp)
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{ alternative: lfence on SSE capable CPUs }
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{$endif CPUX86_HAS_SSE2}
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end;
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procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
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@ -1510,14 +1513,19 @@ end;
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procedure ReadWriteBarrier;assembler;nostackframe;
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asm
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{$ifdef CPUX86_HAS_SSE2}
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mfence
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{$else CPUX86_HAS_SSE2}
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lock
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addl $0,0(%esp)
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{ alternative: mfence on SSE capable CPUs }
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{$endif CPUX86_HAS_SSE2}
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end;
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procedure WriteBarrier;assembler;nostackframe;
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asm
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{ no write reordering on intel CPUs (yet) }
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{$ifdef CPUX86_HAS_SSEUNIT}
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sfence
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{$endif CPUX86_HAS_SSEUNIT}
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end;
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{$endif}
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