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* patch by J. Gareth Moreton: More Peephole optimizations for AND and MOV
git-svn-id: trunk@39242 -
This commit is contained in:
florian
parent
7fcec8460f
commit
0d168796d7
@ -1128,31 +1128,6 @@ unit aoptx86;
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{ remove mov reg1,reg1? }
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if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^)
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{$ifdef x86_64}
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{ Exceptional case:
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if for example, "mov %eax,%eax" is followed by a command that then
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reads %rax, then mov actually has the effect of zeroing the upper
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32 bits of the register and hence is not a null operation. [Kit]
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}
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and not (
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(hp1).typ = ait_instruction) and
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(taicpu(hp1).opsize = S_Q) and
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(taicpu(hp1).ops > 0) and
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(
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(
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg) = getsupreg(taicpu(p).oper[0]^.reg))
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)
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or
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(
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(taicpu(hp1).opcode in [A_IMUL, A_IDIV]) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(getsupreg(taicpu(hp1).oper[1]^.reg) = getsupreg(taicpu(p).oper[0]^.reg))
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)
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)
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)
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{$endif x86_64}
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then
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begin
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DebugMsg(SPeepholeOptimization + 'Mov2Nop done',p);
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@ -2261,12 +2236,51 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass2MOV(var p : tai) : boolean;
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var
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TmpUsedRegs : TAllUsedRegs;
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hp1,hp2: tai;
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hp1,hp2,hp3: tai;
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begin
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Result:=false;
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if MatchOpType(taicpu(p),top_reg,top_reg) and
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GetNextInstruction(p, hp1) and
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{$ifdef x86_64}
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MatchInstruction(hp1,A_MOVZX,A_MOVSX,A_MOVSXD,[]) and
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{$else x86_64}
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MatchInstruction(hp1,A_MOVZX,A_MOVSX,[]) and
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{$endif x86_64}
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MatchOpType(taicpu(hp1),top_reg,top_reg) and
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(taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
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{ mov reg1, reg2 mov reg1, reg2
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movzx/sx reg2, reg3 to movzx/sx reg1, reg3}
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begin
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taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
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DebugMsg(SPeepholeOptimization + 'mov %reg1,%reg2; movzx/sx %reg2,%reg3 -> mov %reg1,%reg2;movzx/sx %reg1,%reg3',p);
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{ Don't remove the MOV command without first checking that reg2 isn't used afterwards,
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or unless supreg(reg3) = supreg(reg2)). [Kit] }
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CopyUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
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if (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) or
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not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)
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then
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begin
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asml.remove(p);
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p.free;
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p := hp1;
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Result:=true;
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end;
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ReleaseUsedRegs(TmpUsedRegs);
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exit;
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end
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else if MatchOpType(taicpu(p),top_reg,top_reg) and
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GetNextInstruction(p, hp1) and
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{$ifdef x86_64}
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MatchInstruction(hp1,[A_MOV,A_MOVZX,A_MOVSX,A_MOVSXD],[]) and
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{$else x86_64}
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MatchInstruction(hp1,A_MOV,A_MOVZX,A_MOVSX,[]) and
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{$endif x86_64}
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MatchOpType(taicpu(hp1),top_ref,top_reg) and
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((taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg)
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or
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@ -2350,6 +2364,100 @@ unit aoptx86;
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p := hp1
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end;
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ReleaseUsedRegs(TmpUsedRegs);
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Exit;
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{$ifdef x86_64}
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end
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else if (taicpu(p).opsize = S_L) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_MOV,[]) and
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(taicpu(hp1).opsize = S_L) and
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(taicpu(hp1).oper[1]^.typ = top_reg)
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) and (
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GetNextInstruction(hp1, hp2) and
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(taicpu(hp2).opsize = S_Q) and
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(
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(
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MatchInstruction(hp2, A_ADD,[]) and
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(taicpu(hp2).opsize = S_Q) and
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(taicpu(hp2).oper[0]^.typ = top_reg) and (taicpu(hp2).oper[1]^.typ = top_reg) and
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(
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(
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(getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) and
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(getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
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) or (
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(getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
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)
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)
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) or (
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MatchInstruction(hp2, A_LEA,[]) and
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(taicpu(hp2).oper[0]^.ref^.offset = 0) and
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(taicpu(hp2).oper[0]^.ref^.scalefactor <= 1) and
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(
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(
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(getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(p).oper[1]^.reg)) and
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(getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(hp1).oper[1]^.reg))
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) or (
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(getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(p).oper[1]^.reg))
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)
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) and (
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(
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(getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
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) or (
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(getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
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)
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)
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)
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)
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) and (
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GetNextInstruction(hp2, hp3) and
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MatchInstruction(hp3, A_SHR,[]) and
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(taicpu(hp3).opsize = S_Q) and
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(taicpu(hp3).oper[0]^.typ = top_const) and (taicpu(hp2).oper[1]^.typ = top_reg) and
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(taicpu(hp3).oper[0]^.val = 1) and
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(taicpu(hp3).oper[1]^.reg = taicpu(hp2).oper[1]^.reg)
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) then
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begin
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{ Change movl x, reg1d movl x, reg1d
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movl y, reg2d movl y, reg2d
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addq reg2q,reg1q or leaq (reg1q,reg2q),reg1q
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shrq $1, reg1q shrq $1, reg1q
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( reg1d and reg2d can be switched around in the first two instructions )
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To movl x, reg1d
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addl y, reg1d
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rcrl $1, reg1d
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This corresponds to the common expression (x + y) shr 1, where
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x and y are Cardinals (replacing "shr 1" with "div 2" produces
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smaller code, but won't account for x + y causing an overflow). [Kit]
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}
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if (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) then
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{ Change first MOV command to have the same register as the final output }
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taicpu(p).oper[1]^.reg := taicpu(hp1).oper[1]^.reg
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else
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taicpu(hp1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
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{ Change second MOV command to an ADD command. This is easier than
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converting the existing command because it means we don't have to
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touch 'y', which might be a complicated reference, and also the
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fact that the third command might either be ADD or LEA. [Kit] }
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taicpu(hp1).opcode := A_ADD;
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{ Delete old ADD/LEA instruction }
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asml.remove(hp2);
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hp2.free;
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{ Convert "shrq $1, reg1q" to "rcr $1, reg1d" }
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taicpu(hp3).opcode := A_RCR;
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taicpu(hp3).changeopsize(S_L);
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setsubreg(taicpu(hp3).oper[1]^.reg, R_SUBD);
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{$endif x86_64}
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end;
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end;
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@ -2909,140 +3017,162 @@ unit aoptx86;
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begin
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Result:=false;
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if not(GetNextInstruction(p, hp1)) then
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exit;
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if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_AND,[]) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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{ the second register must contain the first one, so compare their subreg types }
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(getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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(abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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{ change
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and const1, reg
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and const2, reg
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to
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and (const1 and const2), reg
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}
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if GetNextInstruction(p, hp1) then
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begin
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taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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asml.remove(p);
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p.Free;
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p:=hp1;
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Result:=true;
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exit;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_MOVZX,[]) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ]))
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{$endif x86_64}
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) then
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if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_AND,[]) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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{ the second register must contain the first one, so compare their subreg types }
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(getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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(abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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{ change
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and const1, reg
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and const2, reg
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to
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and (const1 and const2), reg
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}
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
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then
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begin
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{ Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
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32-bit register to a 64-bit register, or even a version called MOVZXD, so
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code that tests for the presence of AND 0xffffffff followed by MOVZX is
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wasted, and is indictive of a compiler bug if it were triggered. [Kit]
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NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
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}
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DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
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asml.remove(hp1);
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hp1.free;
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end;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_SHL,[]) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
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begin
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{ get length of potential and mask }
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MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
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{ really a mask? }
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if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
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{ unmasked part shifted out? }
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((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
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begin
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DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
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{ take care of the register (de)allocs following p }
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UpdateUsedRegs(tai(p.next));
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taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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asml.remove(p);
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p.free;
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p.Free;
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p:=hp1;
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Result:=true;
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exit;
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end;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_MOVSX{$ifdef x86_64},A_MOVSXD{$endif x86_64},[]) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ,S_LQ]))
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{$endif x86_64}
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) then
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7f)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7fff)=taicpu(p).oper[0]^.val))
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{$ifdef x86_64}
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or
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(((taicpu(hp1).opsize)=S_LQ) and
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((taicpu(p).oper[0]^.val and $7fffffff)=taicpu(p).oper[0]^.val)
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)
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{$endif x86_64}
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then
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begin
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DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
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asml.remove(hp1);
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hp1.free;
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end;
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end
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else if (taicpu(p).oper[1]^.typ = top_reg) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).is_jmp) and
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(taicpu(hp1).opcode<>A_JMP) and
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not(RegInUsedRegs(taicpu(p).oper[1]^.reg,UsedRegs)) then
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{ change
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and x, reg
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jxx
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to
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test x, reg
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jxx
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if reg is deallocated before the
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jump, but only if it's a conditional jump (PFV)
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}
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taicpu(p).opcode := A_TEST;
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_MOVZX,[]) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ]))
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{$endif x86_64}
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) then
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
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then
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begin
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{ Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
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32-bit register to a 64-bit register, or even a version called MOVZXD, so
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code that tests for the presence of AND 0xffffffff followed by MOVZX is
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wasted, and is indictive of a compiler bug if it were triggered. [Kit]
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|
||||
NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
|
||||
}
|
||||
DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
|
||||
|
||||
asml.remove(hp1);
|
||||
hp1.free;
|
||||
Exit;
|
||||
end;
|
||||
end
|
||||
else if MatchOpType(taicpu(p),top_const,top_reg) and
|
||||
MatchInstruction(hp1,A_SHL,[]) and
|
||||
MatchOpType(taicpu(hp1),top_const,top_reg) and
|
||||
(getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
|
||||
begin
|
||||
{ get length of potential and mask }
|
||||
MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
|
||||
|
||||
{ really a mask? }
|
||||
if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
|
||||
{ unmasked part shifted out? }
|
||||
((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
|
||||
|
||||
{ take care of the register (de)allocs following p }
|
||||
UpdateUsedRegs(tai(p.next));
|
||||
asml.remove(p);
|
||||
p.free;
|
||||
p:=hp1;
|
||||
Result:=true;
|
||||
exit;
|
||||
end;
|
||||
end
|
||||
else if MatchOpType(taicpu(p),top_const,top_reg) and
|
||||
MatchInstruction(hp1,A_MOVSX{$ifdef x86_64},A_MOVSXD{$endif x86_64},[]) and
|
||||
(taicpu(hp1).oper[0]^.typ = top_reg) and
|
||||
MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
|
||||
(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
|
||||
(((taicpu(p).opsize=S_W) and
|
||||
(taicpu(hp1).opsize=S_BW)) or
|
||||
((taicpu(p).opsize=S_L) and
|
||||
(taicpu(hp1).opsize in [S_WL,S_BL]))
|
||||
{$ifdef x86_64}
|
||||
or
|
||||
((taicpu(p).opsize=S_Q) and
|
||||
(taicpu(hp1).opsize in [S_BQ,S_WQ,S_LQ]))
|
||||
{$endif x86_64}
|
||||
) then
|
||||
begin
|
||||
if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
|
||||
((taicpu(p).oper[0]^.val and $7f)=taicpu(p).oper[0]^.val)
|
||||
) or
|
||||
(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
|
||||
((taicpu(p).oper[0]^.val and $7fff)=taicpu(p).oper[0]^.val))
|
||||
{$ifdef x86_64}
|
||||
or
|
||||
(((taicpu(hp1).opsize)=S_LQ) and
|
||||
((taicpu(p).oper[0]^.val and $7fffffff)=taicpu(p).oper[0]^.val)
|
||||
)
|
||||
{$endif x86_64}
|
||||
then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
|
||||
asml.remove(hp1);
|
||||
hp1.free;
|
||||
Exit;
|
||||
end;
|
||||
end
|
||||
else if (taicpu(p).oper[1]^.typ = top_reg) and
|
||||
(hp1.typ = ait_instruction) and
|
||||
(taicpu(hp1).is_jmp) and
|
||||
(taicpu(hp1).opcode<>A_JMP) and
|
||||
not(RegInUsedRegs(taicpu(p).oper[1]^.reg,UsedRegs)) then
|
||||
begin
|
||||
{ change
|
||||
and x, reg
|
||||
jxx
|
||||
to
|
||||
test x, reg
|
||||
jxx
|
||||
if reg is deallocated before the
|
||||
jump, but only if it's a conditional jump (PFV)
|
||||
}
|
||||
taicpu(p).opcode := A_TEST;
|
||||
Exit;
|
||||
end;
|
||||
end;
|
||||
|
||||
{ Lone AND tests }
|
||||
if MatchOpType(taicpu(p),top_const,top_reg) then
|
||||
begin
|
||||
{
|
||||
- Convert and $0xFF,reg to and reg,reg if reg is 8-bit
|
||||
- Convert and $0xFFFF,reg to and reg,reg if reg is 16-bit
|
||||
- Convert and $0xFFFFFFFF,reg to and reg,reg if reg is 32-bit
|
||||
}
|
||||
if ((taicpu(p).oper[0]^.val = $FF) and (taicpu(p).opsize = S_B)) or
|
||||
((taicpu(p).oper[0]^.val = $FFFF) and (taicpu(p).opsize = S_W)) or
|
||||
((taicpu(p).oper[0]^.val = $FFFFFFFF) and (taicpu(p).opsize = S_L)) then
|
||||
begin
|
||||
taicpu(p).loadreg(0, taicpu(p).oper[1]^.reg)
|
||||
end;
|
||||
end;
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user