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* first bunch of adaptions of arm compiler for new register type

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This commit is contained in:
florian 2003-09-04 00:15:28 +00:00
parent 610cbec252
commit 0d3832776f
13 changed files with 541 additions and 565 deletions
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12
compiler/aasmtai.pas
View File

@ -451,7 +451,7 @@ interface
function spill_registers(list:Taasmoutput;
rgget:Trggetproc;
rgunget:Trgungetproc;
r:Tsuperregisterset;
r:tsuperregisterset;
var unusedregsint:Tsuperregisterset;
const spilltemplist:Tspill_temp_list):boolean;virtual;
function spilling_decode_loadstore(op: tasmop; var counterpart: tasmop; var wasload: boolean): boolean;virtual;abstract;
@ -2080,9 +2080,8 @@ implementation
Top_shifterop:
begin
so:=Taicpu_abstract(p).oper[i].shifterop;
if so^.rs.number<>NR_NO then
so^.rs.number:=(so^.rs.number and $ff) or
(table[so^.rs.number shr 8] shl 8);
if so^.rs<>NR_NO then
setsupreg(so^.rs,table[getsupreg(so^.rs)]);
end;
{$endif arm}
end;
@ -2105,7 +2104,10 @@ implementation
end.
{
$Log$
Revision 1.37 2003-09-03 15:55:00 peter
Revision 1.38 2003-09-04 00:15:28 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.37 2003/09/03 15:55:00 peter
* NEWRA branch merged
Revision 1.36 2003/09/03 11:18:36 florian

7
compiler/aggas.pas
View File

@ -87,7 +87,7 @@ implementation
,itppcgas
{$endif}
{$ifdef arm}
,agarmgas
,itarmgas
{$endif}
;
@ -828,7 +828,10 @@ var
end.
{
$Log$
Revision 1.32 2003-09-03 19:35:24 peter
Revision 1.33 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.32 2003/09/03 19:35:24 peter
* powerpc compiles again
Revision 1.31 2003/09/03 15:55:00 peter

159
compiler/arm/aasmcpu.pas
View File

@ -29,7 +29,7 @@ interface
uses
cclasses,aasmtai,
aasmbase,globals,verbose,
cpubase,cpuinfo;
cpubase,cpuinfo,cginfo;
const
{ "mov reg,reg" source operand number }
@ -42,7 +42,7 @@ uses
oppostfix : TOpPostfix;
roundingmode : troundingmode;
procedure loadshifterop(opidx:longint;const so:tshifterop);
procedure loadregset(opidx:longint;const s:tsupregset);
procedure loadregset(opidx:longint;const s:tsuperregisterset);
constructor op_none(op : tasmop);
constructor op_reg(op : tasmop;_op1 : tregister);
@ -51,28 +51,16 @@ uses
constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
constructor op_reg_const(op:tasmop; _op1: tregister; _op2: longint);
constructor op_reg_regset(op:tasmop; _op1: tregister; _op2: tsupregset);
constructor op_const_const(op : tasmop;_op1,_op2 : longint);
constructor op_reg_regset(op:tasmop; _op1: tregister; _op2: tsuperregisterset);
constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: Longint);
constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
constructor op_const_reg_reg(op : tasmop;_op1 : longint;_op2, _op3 : tregister);
constructor op_const_reg_const(op : tasmop;_op1 : longint;_op2 : tregister;_op3 : longint);
constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
constructor op_reg_reg_reg_const_const(op : tasmop;_op1,_op2,_op3 : tregister;_op4,_op5 : Longint);
constructor op_reg_reg_const_const_const(op : tasmop;_op1,_op2 : tregister;_op3,_op4,_op5 : Longint);
{ this is for Jmp instructions }
constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
constructor op_const_const_sym(op : tasmop;_op1,_op2 : longint;_op3: tasmsymbol);
constructor op_sym(op : tasmop;_op1 : tasmsymbol);
constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
@ -84,8 +72,8 @@ uses
function spill_registers(list:Taasmoutput;
rgget:Trggetproc;
rgunget:Trgungetproc;
r:Tsupregset;
var unusedregsint:Tsupregset;
r:tsuperregisterset;
var unusedregsint:tsuperregisterset;
const spilltemplist:Tspill_temp_list):boolean; override;
end;
@ -124,7 +112,7 @@ implementation
end;
procedure taicpu.loadregset(opidx:longint;const s:tsupregset);
procedure taicpu.loadregset(opidx:longint;const s:tsuperregisterset);
begin
if opidx>=ops then
ops:=opidx+1;
@ -151,8 +139,6 @@ implementation
constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031207);
ops:=1;
loadreg(0,_op1);
end;
@ -169,10 +155,6 @@ implementation
constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031205);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031206);
ops:=2;
loadreg(0,_op1);
loadreg(1,_op2);
@ -182,19 +164,15 @@ implementation
constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: longint);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031208);
ops:=2;
loadreg(0,_op1);
loadconst(1,aword(_op2));
end;
constructor taicpu.op_reg_regset(op:tasmop; _op1: tregister; _op2: tsupregset);
constructor taicpu.op_reg_regset(op:tasmop; _op1: tregister; _op2: tsuperregisterset);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031208);
ops:=2;
loadreg(0,_op1);
loadregset(1,_op2);
@ -204,32 +182,15 @@ implementation
constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031210);
ops:=2;
loadreg(0,_op1);
loadref(1,_op2);
end;
constructor taicpu.op_const_const(op : tasmop;_op1,_op2 : longint);
begin
inherited create(op);
ops:=2;
loadconst(0,aword(_op1));
loadconst(1,aword(_op2));
end;
constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031211);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031212);
if (_op3.enum = R_INTREGISTER) and (_op3.number = NR_NO) then
internalerror(2003031213);
ops:=3;
loadreg(0,_op1);
loadreg(1,_op2);
@ -240,10 +201,6 @@ implementation
constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: Longint);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031214);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031215);
ops:=3;
loadreg(0,_op1);
loadreg(1,_op2);
@ -254,10 +211,6 @@ implementation
constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031216);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031217);
ops:=3;
loadreg(0,_op1);
loadreg(1,_op2);
@ -268,10 +221,6 @@ implementation
constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031218);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031219);
ops:=3;
loadreg(0,_op1);
loadreg(1,_op2);
@ -279,39 +228,9 @@ implementation
end;
constructor taicpu.op_const_reg_reg(op : tasmop;_op1 : longint;_op2, _op3 : tregister);
begin
inherited create(op);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031221);
if (_op3.enum = R_INTREGISTER) and (_op3.number = NR_NO) then
internalerror(2003031220);
ops:=3;
loadconst(0,aword(_op1));
loadreg(1,_op2);
loadreg(2,_op3);
end;
constructor taicpu.op_const_reg_const(op : tasmop;_op1 : longint;_op2 : tregister;_op3 : longint);
begin
inherited create(op);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031222);
ops:=3;
loadconst(0,aword(_op1));
loadreg(1,_op2);
loadconst(2,aword(_op3));
end;
constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(200308233);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(200308233);
ops:=3;
loadreg(0,_op1);
loadreg(1,_op2);
@ -319,59 +238,6 @@ implementation
end;
constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031223);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031224);
if (_op3.enum = R_INTREGISTER) and (_op3.number = NR_NO) then
internalerror(2003031225);
if (_op4.enum = R_INTREGISTER) and (_op4.number = NR_NO) then
internalerror(2003031226);
ops:=4;
loadreg(0,_op1);
loadreg(1,_op2);
loadreg(2,_op3);
loadreg(3,_op4);
end;
constructor taicpu.op_reg_reg_reg_const_const(op : tasmop;_op1,_op2,_op3 : tregister;_op4,_op5 : Longint);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031232);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031233);
if (_op3.enum = R_INTREGISTER) and (_op3.number = NR_NO) then
internalerror(2003031233);
ops:=5;
loadreg(0,_op1);
loadreg(1,_op2);
loadreg(2,_op3);
loadconst(3,cardinal(_op4));
loadconst(4,cardinal(_op5));
end;
constructor taicpu.op_reg_reg_const_const_const(op : tasmop;_op1,_op2 : tregister;_op3,_op4,_op5 : Longint);
begin
inherited create(op);
if (_op1.enum = R_INTREGISTER) and (_op1.number = NR_NO) then
internalerror(2003031232);
if (_op2.enum = R_INTREGISTER) and (_op2.number = NR_NO) then
internalerror(2003031233);
ops:=5;
loadreg(0,_op1);
loadreg(1,_op2);
loadconst(2,aword(_op3));
loadconst(3,cardinal(_op4));
loadconst(4,cardinal(_op5));
end;
constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
begin
inherited create(op);
@ -443,14 +309,14 @@ implementation
function taicpu.spill_registers(list:Taasmoutput;
rgget:Trggetproc;
rgunget:Trgungetproc;
r:Tsupregset;
var unusedregsint:Tsupregset;
r:tsuperregisterset;
var unusedregsint:tsuperregisterset;
const spilltemplist:Tspill_temp_list): boolean;
function get_insert_pos(p:Tai;huntfor1,huntfor2,huntfor3:Tsuperregister):Tai;
var back:Tsupregset;
var back:tsuperregisterset;
begin
back:=unusedregsint;
@ -749,7 +615,10 @@ implementation
end.
{
$Log$
Revision 1.8 2003-09-03 11:18:37 florian
Revision 1.9 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.8 2003/09/03 11:18:37 florian
* fixed arm concatcopy
+ arm support in the common compiler sources added
* moved some generic cg code around

260
compiler/arm/agarmgas.pas
View File

@ -32,7 +32,8 @@ unit agarmgas;
uses
aasmtai,
aggas,
cpubase;
cpubase,
cginfo;
type
PARMGNUAssembler=^TARMGNUAssembler;
@ -40,24 +41,18 @@ unit agarmgas;
procedure WriteInstruction(hp : tai);override;
end;
var
gas_reg2str : reg2strtable;
const
gas_shiftmode2str : array[tshiftmode] of string[3] = (
'','lsl','lsr','asr','ror','rrx');
function gas_regnum_search(const s:string):Tnewregister;
function gas_regname(const r:Tnewregister):string;
implementation
uses
cutils,globals,verbose,
systems,
assemble,
aasmcpu;
aasmcpu,
itarmgas;
const
as_arm_gas_info : tasminfo =
@ -83,26 +78,23 @@ unit agarmgas;
function getreferencestring(var ref : treference) : string;
var
s : string;
nobase,noindex : boolean;
begin
with ref do
begin
inc(offset,offsetfixup);
noindex:=(index.enum=R_NO) or ((index.enum=R_INTREGISTER) and (index.number=NR_NO));
{$ifdef extdebug}
nobase:=(base.enum=R_NO) or ((base.enum=R_INTREGISTER) and (base.number=NR_NO));
//!!!! if nobase then
//!!!! internalerror(200308292);
if base=NR_NO then
internalerror(200308292);
// !!! if (not(noindex) or (shiftmode<>SM_None)) and ((offset<>0) or (symbol<>nil)) then
// !!! internalerror(200308293);
if ((index<>NR_NO) or (shiftmode<>SM_None)) and ((offset<>0) or (symbol<>nil)) then
internalerror(200308293);
{$endif extdebug}
if assigned(symbol) then
begin
// if (base.enum<>R_NO) and not(is_pc(base)) then
// internalerror(200309011);
if (base<>NR_NO) and not(is_pc(base)) then
internalerror(200309011);
s:=symbol.name;
if offset<0 then
s:=s+tostr(offset)
@ -111,23 +103,17 @@ unit agarmgas;
end
else
begin
if base.enum=R_INTREGISTER then
s:='['+gas_regname(base.number)
else
s:='['+gas_reg2str[base.enum];
s:='['+gas_regname(base);
if addressmode=AM_POSTINDEXED then
s:=s+']';
if not(noindex) then
if index<>NR_NO then
begin
if signindex<0 then
s:=s+', -'
else
s:=s+', ';
if index.enum=R_INTREGISTER then
s:=s+gas_regname(index.number)
else
s:=s+gas_reg2str[index.enum];
s:=s+gas_regname(index);
if shiftmode<>SM_None then
s:=s+' ,'+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
@ -145,116 +131,58 @@ unit agarmgas;
end;
function getopstr_jmp(const o:toper) : string;
var
hs : string;
begin
case o.typ of
top_reg :
begin
if (o.reg.enum < R_R0) or (o.reg.enum > lastreg) then
internalerror(200303121);
getopstr_jmp:=std_reg2str[o.reg.enum];
end;
top_shifterop:
begin
end;
{ no top_ref jumping for powerpc }
top_const :
getopstr_jmp:='#'+tostr(o.val);
top_symbol :
begin
hs:=o.sym.name;
if o.symofs>0 then
hs:=hs+'+'+tostr(o.symofs)
else
if o.symofs<0 then
hs:=hs+tostr(o.symofs);
getopstr_jmp:=hs;
end;
top_none:
getopstr_jmp:='';
else
{$ifndef testing}
internalerror(2002070603);
{$else testing}
begin
writeln('internalerror 10001');
halt(1);
end;
{$endif testing}
end;
end;
const
shiftmode2str: array[tshiftmode] of string[3] = ('','lsl','lsr','asr','ror','rrx');
function getopstr(const o:toper) : string;
var
hs : string;
first : boolean;
r : tnewregister;
begin
case o.typ of
top_reg:
begin
if o.reg.enum=R_INTREGISTER then
getopstr:=gas_regname(o.reg.number)
else
getopstr:=gas_reg2str[o.reg.enum];
end;
top_shifterop:
begin
if (o.shifterop^.rs.enum<>R_NO) and (o.shifterop^.shiftimm=0) then
begin
if o.shifterop^.rs.enum=R_INTREGISTER then
getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs.number)
else
getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_reg2str[o.shifterop^.rs.enum];
end
else if (o.shifterop^.rs.enum=R_NO) then
getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
else internalerror(200308282);
end;
top_const:
getopstr:='#'+tostr(longint(o.val));
top_regset:
begin
getopstr:='{';
first:=true;
for r:=RS_R0 to RS_R15 do
if r in o.regset then
begin
if not(first) then
getopstr:=getopstr+',';
getopstr:=getopstr+'r'+tostr(r-RS_R0);
first:=false;
end;
getopstr:=getopstr+'}';
end;
top_ref:
getopstr:=getreferencestring(o.ref^);
top_symbol:
begin
hs:=o.sym.name;
if o.symofs>0 then
hs:=hs+'+'+tostr(o.symofs)
else
if o.symofs<0 then
hs:=hs+tostr(o.symofs);
getopstr:=hs;
end;
else
{$ifndef testing}
internalerror(2002070604);
{$else testing}
begin
writeln('internalerror 10001');
halt(1);
end;
{$endif testing}
var
hs : string;
first : boolean;
r : tregister;
begin
case o.typ of
top_reg:
getopstr:=gas_regname(o.reg);
top_shifterop:
begin
if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
else if (o.shifterop^.rs=NR_NO) then
getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
else internalerror(200308282);
end;
top_const:
getopstr:='#'+tostr(longint(o.val));
top_regset:
begin
getopstr:='{';
first:=true;
for r:=RS_R0 to RS_R15 do
if r in o.regset then
begin
if not(first) then
getopstr:=getopstr+',';
getopstr:=getopstr+gas_regname(newreg(R_INTREGISTER,r,R_SUBWHOLE));
first:=false;
end;
getopstr:=getopstr+'}';
end;
top_ref:
getopstr:=getreferencestring(o.ref^);
top_symbol:
begin
hs:=o.sym.name;
if o.symofs>0 then
hs:=hs+'+'+tostr(o.symofs)
else
if o.symofs<0 then
hs:=hs+tostr(o.symofs);
getopstr:=hs;
end;
else
internalerror(2002070604);
end;
end;
end;
Procedure TARMGNUAssembler.WriteInstruction(hp : tai);
var op: TAsmOp;
@ -263,74 +191,32 @@ unit agarmgas;
sep: string[3];
begin
op:=taicpu(hp).opcode;
{
if is_calljmp(op) then
s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix];
if taicpu(hp).ops<>0 then
begin
{ direct BO/BI in op[0] and op[1] not supported, put them in condition! }
case op of
A_B,A_BA,A_BL,A_BLA:
s:=#9+op2str[op]+#9;
A_BCTR,A_BCTRL,A_BLR,A_BLRL:
s:=#9+op2str[op]
else
s:=cond2str(op,taicpu(hp).condition)+',';
end;
if (taicpu(hp).oper[0].typ <> top_none) then
s:=s+getopstr_jmp(taicpu(hp).oper[0]);
end
else
}
{ process operands }
begin
s:=#9+std_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix];
if taicpu(hp).ops<>0 then
sep:=#9;
for i:=0 to taicpu(hp).ops-1 do
begin
{
if not is_calljmp(op) then
sep:=','
else
}
sep:=#9;
for i:=0 to taicpu(hp).ops-1 do
begin
// debug code
// writeln(s);
// writeln(taicpu(hp).fileinfo.line);
s:=s+sep+getopstr(taicpu(hp).oper[i]);
sep:=',';
end;
// debug code
// writeln(s);
// writeln(taicpu(hp).fileinfo.line);
s:=s+sep+getopstr(taicpu(hp).oper[i]);
sep:=',';
end;
end;
AsmWriteLn(s);
end;
function gas_regnum_search(const s:string):Tnewregister;
begin
end;
function gas_regname(const r:Tnewregister):string;
var s:Tsuperregister;
begin
s:=r shr 8;
if s in [RS_R0..RS_R15] then
gas_regname:='r'+tostr(s-RS_R0)
else
begin
{Generate a systematic name.}
gas_regname:='reg'+tostr(s)+'d';
end;
end;
begin
RegisterAssembler(as_arm_gas_info,TARMGNUAssembler);
gas_reg2str:=std_reg2str;
end.
{
$Log$
Revision 1.8 2003-09-03 19:10:30 florian
Revision 1.9 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.8 2003/09/03 19:10:30 florian
* initial revision of new register naming
Revision 1.7 2003/09/01 15:11:16 florian

94
compiler/arm/armreg.dat Normal file
View File

@ -0,0 +1,94 @@
;
; $Id$
;
; ARM registers
;
; layout
; <name>,<type>,<value>,<stdname>,<stabidx>,<ot value>
;
NO,$00,$00,INVALID,-1
; Integer registers
R0,$01,$00,r0,0
R1,$01,$01,r1,1
R2,$01,$02,r2,2
R3,$01,$03,r3,3
R4,$01,$04,r4,4
R5,$01,$05,r5,5
R6,$01,$06,r6,6
R7,$01,$07,r7,7
R8,$01,$08,r8,8
R9,$01,$09,r9,9
R10,$01,$0a,r10,10
R11,$01,$0b,r11,11
R12,$01,$0c,r12,12
R13,$01,$0d,r13,13
R14,$01,$0e,r14,14
R15,$01,$0f,r15,15
; Float registers
F0,$02,$00,f0,32
F1,$02,$01,f1,32
F2,$02,$02,f2,32
F3,$02,$03,f3,32
F4,$02,$04,f4,32
F5,$02,$05,f5,32
F6,$02,$06,f6,32
F7,$02,$07,f7,32
; MM registers
S0,$02,$00,s0,0
S1,$02,$00,s1,0
D0,$02,$00,d0,0
S2,$02,$00,s2,0
S3,$02,$00,s3,0
D1,$02,$00,d1,0
S4,$02,$00,s4,0
S5,$02,$00,s5,0
D2,$02,$00,d2,0
S6,$02,$00,s6,0
S7,$02,$00,s7,0
D3,$02,$00,d3,0
S8,$02,$00,s8,0
S9,$02,$00,s9,0
D4,$02,$00,d4,0
S10,$02,$00,s10,0
S11,$02,$00,s11,0
D5,$02,$00,d5,0
S12,$02,$00,s12,0
S13,$02,$00,s13,0
D6,$02,$00,d6,0
S14,$02,$00,s14,0
S15,$02,$00,s15,0
D7,$02,$00,d7,0
S16,$02,$00,s16,0
S17,$02,$00,s17,0
D8,$02,$00,d8,0
S18,$02,$00,s18,0
S19,$02,$00,s19,0
D9,$02,$00,d9,0
S20,$02,$00,s20,0
S21,$02,$00,s21,0
D10,$02,$00,d10,0
S22,$02,$00,s22,0
S23,$02,$00,s23,0
D11,$02,$00,d11,0
S24,$02,$00,s24,0
S25,$02,$00,s25,0
D12,$02,$00,d12,0
S26,$02,$00,s26,0
S27,$02,$00,s27,0
D13,$02,$00,d13,0
S28,$02,$00,s28,0
S29,$02,$00,s29,0
D14,$02,$00,d14,0
S30,$02,$00,s20,0
S31,$02,$00,s21,0
D15,$02,$00,d15,0
;
; $Log$
; Revision 1.1 2003-09-04 00:15:29 florian
; * first bunch of adaptions of arm compiler for new register type
;
;

59
compiler/arm/cgcpu.pas
View File

@ -688,8 +688,7 @@ unit cgcpu;
var
ai : taicpu;
begin
ai := Taicpu.op_sym(A_B,l);
ai.SetCondition(flags_to_cond(f));
ai := Taicpu.op_sym_cond(A_B,l,flags_to_cond(f));
ai.is_jmp := true;
list.concat(ai);
end;
@ -699,12 +698,8 @@ unit cgcpu;
var
ai : taicpu;
begin
ai:=Taicpu.op_reg_const(A_MOV,reg,1);
ai.setcondition(flags_to_cond(f));
list.concat(ai);
ai:=Taicpu.op_reg_const(A_MOV,reg,0);
ai.setcondition(inverse_cond[flags_to_cond(f)]);
list.concat(ai);
list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f));
list.concat(setcondition(aicpu.op_reg_const(A_MOV,reg,0),inverse_cond[flags_to_cond(f)]));
end;
@ -719,50 +714,29 @@ unit cgcpu;
begin
LocalSize:=align(LocalSize,4);
rsp.enum:=R_INTREGISTER;
rsp.number:=NR_STACK_POINTER_REG;
a_reg_alloc(list,rsp);
a_reg_alloc(list,NR_STACK_POINTER_REG);
a_reg_alloc(list,NR_FRAME_POINTER_REG);
a_reg_alloc(list,NR_R12);
rfp.enum:=R_INTREGISTER;
rfp.number:=NR_FRAME_POINTER_REG;
a_reg_alloc(list,rfp);
rip.enum:=R_INTREGISTER;
rip.number:=NR_R12;
a_reg_alloc(list,rip);
list.concat(taicpu.op_reg_reg(A_MOV,rip,rsp));
list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
{ restore int registers and return }
list.concat(setoppostfix(taicpu.op_reg_regset(A_STM,rsp,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R12,RS_R15]),PF_FD));
list.concat(taicpu.op_reg_reg_const(A_SUB,rfp,rip,4));
a_reg_alloc(list,rip);
list.concat(taicpu.op_reg_reg_const(A_SUB,NR_FRAME_POINTER_REG,NR_R12,4));
a_reg_alloc(list,NR_R12);
{ allocate necessary stack size }
list.concat(taicpu.op_reg_reg_const(A_SUB,rsp,rsp,LocalSize));
list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
end;
procedure tcgarm.g_return_from_proc(list : taasmoutput;parasize : aword);
var
r1,r2 : tregister;
begin
if (current_procinfo.framepointer.number=NR_STACK_POINTER_REG) then
begin
r1.enum:=R_INTREGISTER;
r1.number:=NR_R15;
r2.enum:=R_INTREGISTER;
r2.number:=NR_R14;
list.concat(taicpu.op_reg_reg(A_MOV,r1,r2));
end
if (current_procinfo.framepointer=NR_STACK_POINTER_REG) then
list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14));
else
begin
r1.enum:=R_INTREGISTER;
r1.number:=NR_R11;
{ restore int registers and return }
list.concat(setoppostfix(taicpu.op_reg_regset(A_LDM,r1,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
end;
{ restore int registers and return }
list.concat(setoppostfix(taicpu.op_reg_regset(A_LDM,NR_R11,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
end;
@ -1127,7 +1101,10 @@ begin
end.
{
$Log$
Revision 1.12 2003-09-03 19:10:30 florian
Revision 1.13 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.12 2003/09/03 19:10:30 florian
* initial revision of new register naming
Revision 1.11 2003/09/03 11:18:37 florian

192
compiler/arm/cpubase.pas
View File

@ -28,18 +28,18 @@ unit cpubase;
{$i fpcdefs.inc}
interface
interface
uses
cutils,cclasses,
globtype,globals,
cpuinfo,
aasmbase,
cginfo
{$ifdef delphi}
,dmisc
{$endif}
;
uses
cutils,cclasses,
globtype,globals,
cpuinfo,
aasmbase,
cginfo
{$ifdef delphi}
,dmisc
{$endif}
;
{*****************************************************************************
@ -69,7 +69,7 @@ uses
{ This should define the array of instructions as string }
op2strtable=array[tasmop] of string[11];
Const
const
{ First value of opcode enumeration }
firstop = low(tasmop);
{ Last value of opcode enumeration }
@ -79,6 +79,10 @@ uses
Registers
*****************************************************************************}
type
{ Number of registers used for indexing in tables }
tregisterindex=0..{$i rarmnor.inc}-1;
const
{ Super registers: }
RS_NONE=$00;
@ -112,11 +116,30 @@ uses
{ Available Registers }
{$i rarmcon.inc}
type
{ Number of registers used for indexing in tables }
tregisterindex=0..{$i rarmnor.inc}-1;
{ Integer Super registers first and last }
{$warning Supreg shall be $00-$1f}
first_int_supreg = RS_R3;
last_int_supreg = RS_R15;
first_int_imreg = $20;
last_int_imreg = $fe;
{ Float Super register first and last }
first_fpu_supreg = $00;
last_fpu_supreg = $07;
first_fpu_imreg = $20;
last_fpu_imreg = $fe;
{ MM Super register first and last }
first_mmx_supreg = RS_INVALID;
last_mmx_supreg = RS_INVALID;
first_mmx_imreg = RS_INVALID;
last_mmx_imreg = RS_INVALID;
{$warning TODO Calculate bsstart}
regnumber_count_bsstart = 64;
const
regnumber_table : array[tregisterindex] of tregister = (
{$i rarmnum.inc}
);
@ -254,7 +277,7 @@ uses
top_ref : (ref:preference);
top_const : (val:aword);
top_symbol : (sym:tasmsymbol;symofs:longint);
top_regset : (regset:set of RS_R0..RS_R15);
top_regset : (regset:tsuperregisterset);
top_shifterop : (shifterop : pshifterop);
end;
@ -346,6 +369,8 @@ uses
{ c_countusableregsxxx = amount of registers in the usableregsxxx set }
maxintregs = 15;
{ to determine how many registers to use for regvars }
maxintscratchregs = 3;
usableregsint = [RS_R4..RS_R10];
c_countusableregsint = 7;
@ -374,38 +399,11 @@ uses
S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
);
{*****************************************************************************
Registers
*****************************************************************************}
const
{ Standard opcode string table (for each tasmop enumeration). The
opcode strings should conform to the names as defined by the
processor manufacturer.
}
std_op2str : op2strtable = (
'','adc','add','and','n','bic','bkpt','b','bl','blx','bx',
'cdp','cdp2','clz','cmn','cmp','eor','ldc','ldc2',
'ldm','ldr','ldrb','ldrd','ldrbt','ldrh','ldrsb',
'ldrsh','ldrt','mcr','mcr2','mcrr','mla','mov',
'mrc','mrc2','mrrc','rs','msr','mul','mvn',
'orr','pld','qadd','qdadd','qdsub','qsub','rsb','rsc',
'sbc','smlal','smull','smul',
'smulw','stc','stc2','stm','str','strb','strbt','strd',
'strh','strt','sub','swi','swp','swpb','teq','tst',
'umlal','umull',
{ FPA coprocessor codes }
'ldf','stf','lfm','sfm','flt','fix','wfs','rfs','rfc',
'adf','dvf','fdv','fml','frd','muf','pol','pw','rdf',
'rmf','rpw','rsf','suf','abs','acs','asn','atn','cos',
'exp','log','lgn','mvf','mnf','nrm','rnd','sin','sqt','tan','urd',
'cmf','cnf'
{ VPA coprocessor codes }
);
{*****************************************************************************
Constants
*****************************************************************************}
const
firstsaveintreg = RS_R4;
lastsaveintreg = RS_R10;
firstsavefpureg = RS_F4;
@ -502,13 +500,14 @@ uses
Helpers
*****************************************************************************}
procedure convert_register_to_enum(var r:Tregister);
function cgsize2subreg(s:Tcgsize):Tsubregister;
function reg2opsize(r:tregister):topsize;
function is_calljmp(o:tasmop):boolean;
procedure inverse_flags(var f: TResFlags);
function flags_to_cond(const f: TResFlags) : TAsmCond;
function supreg_name(r:Tsuperregister):string;
function findreg_by_number(r:Tregister):tregisterindex;
function findreg_by_stdname(const s:string):byte;
function std_regnum_search(const s:string):Tregister;
function std_regname(r:Tregister):string;
procedure shifterop_reset(var so : tshifterop);
function is_pc(const r : tregister) : boolean;
@ -518,13 +517,19 @@ uses
uses
verbose;
procedure convert_register_to_enum(var r:Tregister);
begin
if r.enum = R_INTREGISTER then
r.enum := toldregister(r.number shr 8)
else
internalerror(200308271);
end;
const
std_regname_table : array[tregisterindex] of string[7] = (
{$i rarmstd.inc}
);
regnumber_index : array[tregisterindex] of tregisterindex = (
{$i rarmrni.inc}
);
std_regname_index : array[tregisterindex] of tregisterindex = (
{$i rarmsri.inc}
);
function cgsize2subreg(s:Tcgsize):Tsubregister;
@ -532,11 +537,6 @@ uses
end;
function reg2opsize(r:tregister):topsize;
begin
end;
function is_calljmp(o:tasmop):boolean;
begin
{ This isn't 100% perfect because the arm allows jumps also by writing to PC=R15.
@ -562,23 +562,59 @@ uses
end;
function supreg_name(r:Tsuperregister):string;
const
supreg_names:array[0..last_supreg] of string[3]=
('inv',
'r0' ,'r2', 'r3','r4','r5','r6','r7','r8',
'r8' ,'r9', 'r10','r11','r12','r13','r14','pc'
);
function findreg_by_stdname(const s:string):byte;
var
s : string[4];
i,p : tregisterindex;
begin
if r in [0..last_supreg] then
supreg_name:=supreg_names[r]
{Binary search.}
p:=0;
i:=regnumber_count_bsstart;
repeat
if (p+i<=high(tregisterindex)) and (std_regname_table[std_regname_index[p+i]]<=s) then
p:=p+i;
i:=i shr 1;
until i=0;
if std_regname_table[std_regname_index[p]]=s then
result:=std_regname_index[p]
else
begin
str(r,s);
supreg_name:='reg'+s;
end;
result:=0;
end;
function findreg_by_number(r:Tregister):tregisterindex;
var
i,p : tregisterindex;
begin
{Binary search.}
p:=0;
i:=regnumber_count_bsstart;
repeat
if (p+i<=high(tregisterindex)) and (regnumber_table[regnumber_index[p+i]]<=r) then
p:=p+i;
i:=i shr 1;
until i=0;
if regnumber_table[regnumber_index[p]]=r then
result:=regnumber_index[p]
else
result:=0;
end;
function std_regnum_search(const s:string):Tregister;
begin
result:=regnumber_table[findreg_by_stdname(s)];
end;
function std_regname(r:Tregister):string;
var
p : tregisterindex;
begin
p:=findreg_by_number(r);
if p<>0 then
result:=std_regname_table[p]
else
result:=generic_regname(r);
end;
@ -590,14 +626,16 @@ uses
function is_pc(const r : tregister) : boolean;
begin
is_pc:=((r.enum=R_INTREGISTER) and (r.number=NR_R15))
or (r.enum=R_PC);
is_pc:=(r=NR_R15);
end;
end.
{
$Log$
Revision 1.11 2003-09-03 19:10:30 florian
Revision 1.12 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.11 2003/09/03 19:10:30 florian
* initial revision of new register naming
Revision 1.10 2003/09/01 15:11:16 florian

67
compiler/arm/cpupara.pas
View File

@ -58,15 +58,13 @@ unit cpupara;
else if nr<=4 then
begin
result.loc:=LOC_REGISTER;
result.register.enum:=R_INTREGISTER;
result.register.number:=NR_R0+(nr-1)*(NR_R1-NR_R0);
rg.getexplicitregisterint(list,result.register.number);
result.register:=newreg(R_INTREGISTER,RS_R0+nr,R_SUBWHOLE);
rg.getexplicitregisterint(list,result.register);
end
else
begin
result.loc:=LOC_REFERENCE;
result.reference.index.enum:=R_INTREGISTER;
result.reference.index.number:=NR_STACK_POINTER_REG;
result.reference.index:=NR_STACK_POINTER_REG;
result.reference.offset:=(nr-4)*4;
end;
result.size := OS_INT;
@ -83,8 +81,7 @@ unit cpupara;
internalerror(2003060401)
else if nr<=4 then
begin
r.enum := R_INTREGISTER;
r.number := NR_R0+(nr-1)*(NR_R1-NR_R0);
r:=newreg(R_INTREGISTER,RS_R0+nr,R_SUBWHOLE);
rg.ungetregisterint(list,r);
end;
end;
@ -180,17 +177,16 @@ unit cpupara;
procedure assignintreg;
begin
if nextintreg.number<=NR_R3 then
if nextintreg<=NR_R3 then
begin
paraloc.loc:=LOC_REGISTER;
paraloc.register:=nextintreg;
inc(nextintreg.number,NR_R1-NR_R0);
inc(nextintreg,NR_R1-NR_R0);
end
else
begin
paraloc.loc:=LOC_REFERENCE;
paraloc.reference.index.enum:=R_INTREGISTER;
paraloc.reference.index.number:=NR_STACK_POINTER_REG;
paraloc.reference.index:=NR_STACK_POINTER_REG;
paraloc.reference.offset:=stack_offset;
inc(stack_offset,4);
end;
@ -201,10 +197,9 @@ unit cpupara;
fillchar(nextintreg,sizeof(nextintreg),0);
fillchar(nextfloatreg,sizeof(nextfloatreg),0);
fillchar(nextmmreg,sizeof(nextmmreg),0);
nextintreg.enum:=R_INTREGISTER;
nextintreg.number:=NR_R0;
nextfloatreg.enum:=R_F0;
// nextmmreg:=0;
nextintreg:=RS_R0;
nextfloatreg:=RS_F0;
nextmmreg:=RS_D0;
stack_offset:=0;
{ frame pointer for nested procedures? }
@ -234,23 +229,22 @@ unit cpupara;
if paraloc.size = OS_NO then
paraloc.size := OS_ADDR;
is_64bit := paraloc.size in [OS_64,OS_S64];
if nextintreg.number<=(NR_R3-ord(is_64bit)*(NR_R1-NR_R0)) then
if nextintreg<=(RS_R3-ord(is_64bit)) then
begin
paraloc.loc:=LOC_REGISTER;
if is_64bit then
begin
paraloc.registerhigh:=nextintreg;
inc(nextintreg.number,NR_R1-NR_R0);
inc(nextintreg);
end;
paraloc.registerlow:=nextintreg;
inc(nextintreg.number,NR_R1-NR_R0);
inc(nextintreg);
end
else
begin
nextintreg.number := NR_R4;
nextintreg := RS_R4;
paraloc.loc:=LOC_REFERENCE;
paraloc.reference.index.enum:=R_INTREGISTER;
paraloc.reference.index.number:=NR_STACK_POINTER_REG;
paraloc.reference.index:=NR_STACK_POINTER_REG;
paraloc.reference.offset:=stack_offset;
if not is_64bit then
inc(stack_offset,4)
@ -261,11 +255,11 @@ unit cpupara;
LOC_FPUREGISTER:
begin
paraloc.size:=def_cgsize(paradef);
if nextfloatreg.enum<=R_F3 then
if nextfloatreg<=RS_F3 then
begin
paraloc.loc:=LOC_FPUREGISTER;
paraloc.register:=nextfloatreg;
inc(nextfloatreg.enum);
inc(nextfloatreg);
end
else
begin
@ -284,8 +278,7 @@ unit cpupara;
else
begin
paraloc.loc:=LOC_REFERENCE;
paraloc.reference.index.enum:=R_INTREGISTER;
paraloc.reference.index.number:=NR_STACK_POINTER_REG;
paraloc.reference.index:=NR_STACK_POINTER_REG;
paraloc.reference.offset:=stack_offset;
inc(stack_offset,hp.paratype.def.size);
end;
@ -293,7 +286,7 @@ unit cpupara;
else
internalerror(2002071002);
end;
if side = calleeside then
if side=calleeside then
begin
if (paraloc.loc = LOC_REFERENCE) then
paraloc.reference.offset := tvarsym(hp.parasym).adjusted_address;
@ -308,7 +301,7 @@ unit cpupara;
if p.rettype.def.deftype=floatdef then
begin
paraloc.loc:=LOC_FPUREGISTER;
paraloc.register.enum:=FPU_RESULT_REG;
paraloc.register:=NR_FPU_RESULT_REG;
end
else
{ Return in register? }
@ -316,17 +309,12 @@ unit cpupara;
begin
paraloc.loc:=LOC_REGISTER;
if paraloc.size in [OS_64,OS_S64] then
begin
paraloc.register64.reglo.enum:=R_INTREGISTER;
paraloc.register64.reglo.number:=NR_FUNCTION_RETURN64_LOW_REG;
paraloc.register64.reghi.enum:=R_INTREGISTER;
paraloc.register64.reghi.number:=NR_FUNCTION_RETURN64_HIGH_REG;
end
begin
paraloc.register64.reglo:=NR_FUNCTION_RETURN64_LOW_REG;
paraloc.register64.reghi:=NR_FUNCTION_RETURN64_HIGH_REG;
end
else
begin
paraloc.register.enum:=R_INTREGISTER;
paraloc.register.number:=NR_FUNCTION_RETURN_REG;
end;
paraloc.register:=NR_FUNCTION_RETURN_REG;
end
else
begin
@ -340,7 +328,10 @@ begin
end.
{
$Log$
Revision 1.3 2003-08-27 00:27:56 florian
Revision 1.4 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.3 2003/08/27 00:27:56 florian
+ same procedure as very day: today's work on arm
Revision 1.2 2003/08/16 13:23:01 florian

118
compiler/arm/itarmgas.pas Normal file
View File

@ -0,0 +1,118 @@
{
$Id$
Copyright (c) 1998-2002 by Florian Klaempfl
This unit contains the ARM GAS instruction tables
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit itarmgas;
{$i fpcdefs.inc}
interface
uses
cginfo,cpubase;
const
{ Standard opcode string table (for each tasmop enumeration). The
opcode strings should conform to the names as defined by the
processor manufacturer.
}
gas_op2str : op2strtable = (
'','adc','add','and','n','bic','bkpt','b','bl','blx','bx',
'cdp','cdp2','clz','cmn','cmp','eor','ldc','ldc2',
'ldm','ldr','ldrb','ldrd','ldrbt','ldrh','ldrsb',
'ldrsh','ldrt','mcr','mcr2','mcrr','mla','mov',
'mrc','mrc2','mrrc','rs','msr','mul','mvn',
'orr','pld','qadd','qdadd','qdsub','qsub','rsb','rsc',
'sbc','smlal','smull','smul',
'smulw','stc','stc2','stm','str','strb','strbt','strd',
'strh','strt','sub','swi','swp','swpb','teq','tst',
'umlal','umull',
{ FPA coprocessor codes }
'ldf','stf','lfm','sfm','flt','fix','wfs','rfs','rfc',
'adf','dvf','fdv','fml','frd','muf','pol','pw','rdf',
'rmf','rpw','rsf','suf','abs','acs','asn','atn','cos',
'exp','log','lgn','mvf','mnf','nrm','rnd','sin','sqt','tan','urd',
'cmf','cnf'
{ VPA coprocessor codes }
);
function gas_regnum_search(const s:string):Tregister;
function gas_regname(r:Tregister):string;
implementation
uses
cutils,verbose;
const
gas_regname_table : array[tregisterindex] of string[7] = (
{$i rarmstd.inc}
);
gas_regname_index : array[tregisterindex] of tregisterindex = (
{$i rarmsri.inc}
);
function findreg_by_gasname(const s:string):tregisterindex;
var
i,p : tregisterindex;
begin
{Binary search.}
p:=0;
i:=regnumber_count_bsstart;
repeat
if (p+i<=high(tregisterindex)) and (gas_regname_table[gas_regname_index[p+i]]<=s) then
p:=p+i;
i:=i shr 1;
until i=0;
if gas_regname_table[gas_regname_index[p]]=s then
findreg_by_gasname:=gas_regname_index[p]
else
findreg_by_gasname:=0;
end;
function gas_regnum_search(const s:string):Tregister;
begin
result:=regnumber_table[findreg_by_gasname(s)];
end;
function gas_regname(r:Tregister):string;
var
p : tregisterindex;
begin
p:=findreg_by_number(r);
if p<>0 then
result:=gas_regname_table[p]
else
result:=generic_regname(r);
end;
end.
{
$Log$
Revision 1.1 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
}

43
compiler/arm/radirect.pas
View File

@ -51,31 +51,22 @@ interface
{ parser }
scanner,
{ codegen }
cginfo,
cgbase,
{ constants }
agarmgas,
itarmgas,
cpubase
;
{ checks if a string identifies a register }
{ it should be optimized }
function is_register(const s : string) : boolean;
var
r : toldregister;
function is_register(const s:string):boolean;
begin
is_register:=false;
if length(s)>5 then
exit;
for r:=low(std_reg2str) to high(std_reg2str) do
if std_reg2str[r]=s then
begin
is_register:=true;
exit;
end;
is_register:=false;
if gas_regnum_search(lower(s))<>NR_NO then
is_register:=true;
end;
function assemble : tnode;
function assemble : tnode;
var
retstr,s,hs : string;
c : char;
@ -105,9 +96,7 @@ interface
begin
ende:=false;
framereg.enum:=R_INTREGISTER;
framereg.number:=NR_FRAME_POINTER_REG;
convert_register_to_enum(framereg);
framereg:=NR_FRAME_POINTER_REG;
s:='';
if assigned(current_procinfo.procdef.funcretsym) and
is_fpu(current_procinfo.procdef.rettype.def) then
@ -192,14 +181,11 @@ interface
hs:=tvarsym(sym).mangledname
else
begin
if (tvarsym(sym).reg.enum<>R_NO) then
// until new regallocator stuff settles down
// hs:=gas_reg2str[procinfo.framepointer.enum]
hs:=std_reg2str[framereg.enum]
if (tvarsym(sym).reg<>NR_NO) then
hs:=std_regname(framereg)
else
hs:=tostr(tvarsym(sym).address)+
// '('+gas_reg2str[procinfo.framepointer.enum]+')';
'('+std_reg2str[framereg.enum]+')';
'('+std_regname(framereg)+')';
end;
end
else
@ -221,7 +207,7 @@ interface
{ set offset }
inc(l,current_procinfo.procdef.parast.address_fixup);
// hs:=tostr(l)+'('+gas_reg2str[procinfo.framepointer.enum]+')';
hs:=tostr(l)+'('+std_reg2str[framereg.enum]+')';
hs:=tostr(l)+'('+std_regname(framereg)+')';
if pos(',',s) > 0 then
tvarsym(sym).varstate:=vs_used;
end;
@ -350,7 +336,10 @@ initialization
end.
{
$Log$
Revision 1.3 2003-09-01 15:11:17 florian
Revision 1.4 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.3 2003/09/01 15:11:17 florian
* fixed reference handling
* fixed operand postfix for floating point instructions
* fixed wrong shifter constant handling

64
compiler/arm/rarmrni.inc
View File

@ -1,21 +1,21 @@
{ don't edit, this file is generated from armreg.dat }
0,
1,
66,
67,
68,
69,
70,
71,
72,
41,
42,
43,
44,
45,
46,
47,
48,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
50,
51,
@ -40,6 +40,22 @@
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
66,
67,
68,
69,
70,
71,
72,
57,
58,
59,
@ -48,27 +64,11 @@
62,
63,
64,
49,
65,
18,
2,
19,
3,
20,
4,
21,
5,
22,
6,
23,
7,
24,
8,
9,
10,
11,
12,
13,
14,
15,
16
24

14
compiler/arm/rgcpu.pas
View File

@ -36,12 +36,14 @@ unit rgcpu;
type
trgcpu = class(trgobj)
{
function getexplicitregisterfpu(list : taasmoutput; r : Toldregister) : tregister;override;
procedure ungetregisterfpu(list: taasmoutput; r : tregister; size:TCGsize);override;
procedure cleartempgen; override;
private
private
usedpararegs: Tsupregset;
usedparafpuregs: tregisterset;
}
end;
implementation
@ -49,7 +51,7 @@ unit rgcpu;
uses
cgobj, verbose, cutils;
{
function trgcpu.getexplicitregisterfpu(list : taasmoutput; r : Toldregister) : tregister;
begin
if (r in [R_F0..R_F3]) and
@ -89,14 +91,18 @@ unit rgcpu;
usedparafpuregs := [];
end;
}
initialization
rg := trgcpu.create(last_supreg-first_supreg+1);
rg := trgcpu.create(last_int_supreg-first_int_supreg+1);
end.
{
$Log$
Revision 1.2 2003-08-25 23:20:38 florian
Revision 1.3 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.2 2003/08/25 23:20:38 florian
+ started to implement FPU support for the ARM
* fixed a lot of other things

17
compiler/powerpc/radirect.pas
View File

@ -57,12 +57,12 @@ interface
itppcgas
;
function is_register(const s:string):boolean;
begin
is_register:=false;
if gas_regnum_search(lower(s))<>NR_NO then
is_register:=true;
end;
function is_register(const s:string):boolean;
begin
is_register:=false;
if gas_regnum_search(lower(s))<>NR_NO then
is_register:=true;
end;
function assemble : tnode;
@ -340,7 +340,10 @@ initialization
end.
{
$Log$
Revision 1.17 2003-09-03 19:35:24 peter
Revision 1.18 2003-09-04 00:15:29 florian
* first bunch of adaptions of arm compiler for new register type
Revision 1.17 2003/09/03 19:35:24 peter
* powerpc compiles again
Revision 1.16 2003/06/13 21:19:32 peter