mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-18 17:19:32 +02:00
Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers.
git-svn-id: trunk@28009 -
This commit is contained in:
Jeppe Johansen
parent
c2a29a0dbb
commit
0dc39b5d63
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -7988,6 +7988,8 @@ rtl/embedded/arm/lpc1768.pp svneol=native#text/pascal
|
||||
rtl/embedded/arm/lpc21x4.pp svneol=native#text/plain
|
||||
rtl/embedded/arm/lpc8xx.pp svneol=native#text/pascal
|
||||
rtl/embedded/arm/sc32442b.pp svneol=native#text/pascal
|
||||
rtl/embedded/arm/stm32f0xx.pp svneol=native#text/plain
|
||||
rtl/embedded/arm/stm32f10x_cl.pp svneol=native#text/plain
|
||||
rtl/embedded/arm/stm32f10x_conn.pp svneol=native#text/pascal
|
||||
rtl/embedded/arm/stm32f10x_hd.pp svneol=native#text/pascal
|
||||
rtl/embedded/arm/stm32f10x_ld.pp svneol=native#text/pascal
|
||||
|
||||
@ -182,6 +182,28 @@ Type
|
||||
ct_at91sam7xc256,
|
||||
|
||||
{ STMicroelectronics }
|
||||
ct_stm32f030c6,
|
||||
ct_stm32f030c8,
|
||||
ct_stm32f030f4,
|
||||
ct_stm32f030k6,
|
||||
ct_stm32f030r8,
|
||||
ct_stm32f050c4,
|
||||
ct_stm32f050c6,
|
||||
ct_stm32f050f4,
|
||||
ct_stm32f050f6,
|
||||
ct_stm32f050g4,
|
||||
ct_stm32f050g6,
|
||||
ct_stm32f050k4,
|
||||
ct_stm32f050k6,
|
||||
ct_stm32f051c4,
|
||||
ct_stm32f051c6,
|
||||
ct_stm32f051c8,
|
||||
ct_stm32f051k4,
|
||||
ct_stm32f051k6,
|
||||
ct_stm32f051k8,
|
||||
ct_stm32f051r4,
|
||||
ct_stm32f051r6,
|
||||
ct_stm32f051r8,
|
||||
ct_stm32f100x4, // LD&MD value line, 4=16,6=32,8=64,b=128
|
||||
ct_stm32f100x6,
|
||||
ct_stm32f100x8,
|
||||
@ -214,6 +236,16 @@ Type
|
||||
ct_stm32f107x8, // MD and HD connectivity line, 8=64,B=128,C=256
|
||||
ct_stm32f107xB,
|
||||
ct_stm32f107xC,
|
||||
ct_stm32f105r8,
|
||||
ct_stm32f105rb,
|
||||
ct_stm32f105rc,
|
||||
ct_stm32f105v8,
|
||||
ct_stm32f105vb,
|
||||
ct_stm32f105vc,
|
||||
ct_stm32f107rb,
|
||||
ct_stm32f107rc,
|
||||
ct_stm32f107vb,
|
||||
ct_stm32f107vc,
|
||||
|
||||
{ TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
|
||||
ct_lm3s1110,
|
||||
@ -383,91 +415,91 @@ Const
|
||||
|
||||
{ LPC 11xx Series}
|
||||
(controllertypestr:'LPC1110FD20'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00001000; srambase:$10000000; sramsize:$00000400),
|
||||
(controllertypestr:'LPC1111FDH20/002'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33/101'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33/103'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33/201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1111FHN33/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1111FHN33/203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1111FDH20_002'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33_101'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33_103'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1111FHN33_201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1111FHN33_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1111FHN33_203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
|
||||
(controllertypestr:'LPC1112FD20/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FDH20/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FDH28/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33/101'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33/103'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33/201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN24/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33/203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHI33/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHI33/203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FD20_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FDH20_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FDH28_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33_101'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33_103'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00000800),
|
||||
(controllertypestr:'LPC1112FHN33_201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN24_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHN33_203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHI33_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1112FHI33_203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00001000),
|
||||
|
||||
(controllertypestr:'LPC1113FHN33/201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33/203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FHN33/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FHN33/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FHN33_201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33_203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1113FHN33_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FHN33_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FHN33_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1113FBD48_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00006000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC1114FDH28/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FN28/102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33/201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33/202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33/203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33/333'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000E000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHI33/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHI33/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48/323'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48/333'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000E000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FDH28_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FN28_102'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33_201'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33_202'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33_203'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1114FHN33_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHN33_333'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000E000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHI33_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FHI33_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48_323'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1114FBD48_333'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$0000E000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC1115FBD48/303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1115FBD48_303'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC11C12FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C14FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C12FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C14FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC11C22FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C24FBD48/301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C22FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00004000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11C24FBD48_301'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC11D14FBD100/302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC11D14FBD100_302'; controllerunitstr:'LPC11XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
{LPC 122x Series}
|
||||
(controllertypestr:'LPC1224FBD48/101'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD48/121'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD64/101'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD64/121'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD48_101'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD48_121'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD64_101'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1224FBD64_121'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$0000C000; srambase:$10000000; sramsize:$00001000),
|
||||
|
||||
(controllertypestr:'LPC1225FBD48/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD48/321'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00014000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD64/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD64/321'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00014000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD48_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD48_321'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00014000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD64_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00010000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1225FBD64_321'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00014000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC1226FBD48/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00018000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1226FBD64/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00018000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1226FBD48_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00018000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1226FBD64_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00018000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC1227FBD48/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1227FBD64/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1227FBD48_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1227FBD64_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC12D27FBD100/301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC12D27FBD100_301'; controllerunitstr:'LPC122X'; flashbase:$00000000; flashsize:$00020000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
|
||||
(controllertypestr:'LPC1311FHN33'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1311FHN33/01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
(controllertypestr:'LPC1311FHN33_01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00002000; srambase:$10000000; sramsize:$00001000),
|
||||
|
||||
(controllertypestr:'LPC1313FHN33'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1313FHN33/01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1313FHN33_01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1313FBD48'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1313FBD48/01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1313FBD48_01'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
|
||||
(controllertypestr:'LPC1315FHN33'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
(controllertypestr:'LPC1315FBD48'; controllerunitstr:'LPC13XX'; flashbase:$00000000; flashsize:$00008000; srambase:$10000000; sramsize:$00002000),
|
||||
@ -511,6 +543,30 @@ Const
|
||||
(controllertypestr:'AT91SAM7X256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000),
|
||||
(controllertypestr:'AT91SAM7XC256'; controllerunitstr:'AT91SAM7x256'; flashbase:$00000000; flashsize:$00040000; srambase:$00200000; sramsize:$00010000),
|
||||
|
||||
{ STM32F0 series }
|
||||
(controllertypestr:'STM32F030C6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F030C8'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
|
||||
(controllertypestr:'STM32F030F4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F030K6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F030R8'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
|
||||
(controllertypestr:'STM32F050C4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050C6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050F4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050F6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050G4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050G6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050K4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F050K6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051C4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051C6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051C8'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
|
||||
(controllertypestr:'STM32F051K4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051K6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051K8'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
|
||||
(controllertypestr:'STM32F051R4'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051R6'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F051R8'; controllerunitstr:'STM32F0XX'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
|
||||
|
||||
{ STM32F1 series }
|
||||
(controllertypestr:'STM32F100X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
|
||||
(controllertypestr:'STM32F100X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
|
||||
@ -545,6 +601,17 @@ Const
|
||||
(controllertypestr:'STM32F107XB'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F107XC'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
|
||||
|
||||
(controllertypestr:'STM32F105R8'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F105RB'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F105RC'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F105V8'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F105VB'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F105VC'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F107RB'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F107RC'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F107VB'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
|
||||
(controllertypestr:'STM32F107VC'; controllerunitstr:'STM32F10X_CL'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
|
||||
|
||||
(controllertypestr:'LM3S1110'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000),
|
||||
(controllertypestr:'LM3S1133'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000),
|
||||
(controllertypestr:'LM3S1138'; controllerunitstr:'LM3FURY'; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00004000),
|
||||
|
||||
@ -336,6 +336,29 @@ begin
|
||||
ct_at91sam7x256,
|
||||
ct_at91sam7xc256,
|
||||
|
||||
ct_stm32f030c6,
|
||||
ct_stm32f030c8,
|
||||
ct_stm32f030f4,
|
||||
ct_stm32f030k6,
|
||||
ct_stm32f030r8,
|
||||
ct_stm32f050c4,
|
||||
ct_stm32f050c6,
|
||||
ct_stm32f050f4,
|
||||
ct_stm32f050f6,
|
||||
ct_stm32f050g4,
|
||||
ct_stm32f050g6,
|
||||
ct_stm32f050k4,
|
||||
ct_stm32f050k6,
|
||||
ct_stm32f051c4,
|
||||
ct_stm32f051c6,
|
||||
ct_stm32f051c8,
|
||||
ct_stm32f051k4,
|
||||
ct_stm32f051k6,
|
||||
ct_stm32f051k8,
|
||||
ct_stm32f051r4,
|
||||
ct_stm32f051r6,
|
||||
ct_stm32f051r8,
|
||||
|
||||
ct_stm32f100x4,
|
||||
ct_stm32f100x6,
|
||||
ct_stm32f100x8,
|
||||
@ -368,6 +391,16 @@ begin
|
||||
ct_stm32f107x8,
|
||||
ct_stm32f107xB,
|
||||
ct_stm32f107xC,
|
||||
ct_stm32f105r8,
|
||||
ct_stm32f105rb,
|
||||
ct_stm32f105rc,
|
||||
ct_stm32f105v8,
|
||||
ct_stm32f105vb,
|
||||
ct_stm32f105vc,
|
||||
ct_stm32f107rb,
|
||||
ct_stm32f107rc,
|
||||
ct_stm32f107vb,
|
||||
ct_stm32f107vc,
|
||||
|
||||
{ TI - 64 K Flash, 16 K SRAM Devices }
|
||||
ct_lm3s1110,
|
||||
@ -475,6 +508,13 @@ begin
|
||||
|
||||
Add('}');
|
||||
Add('_stack_top = 0x' + IntToHex(sramsize+srambase,8) + ';');
|
||||
|
||||
// Add Checksum Calculation for LPC Controllers so that the bootloader starts the uploaded binary
|
||||
writeln(controllerunitstr);
|
||||
if (controllerunitstr = 'LPC8xx') or (controllerunitstr = 'LPC11XX') or (controllerunitstr = 'LPC122X') then
|
||||
Add('Startup_Checksum = 0 - (_stack_top + _START + 1 + NonMaskableInt_interrupt + 1 + Hardfault_interrupt + 1);');
|
||||
if (controllerunitstr = 'LPC13XX') then
|
||||
Add('Startup_Checksum = 0 - (_stack_top + _START + 1 + NonMaskableInt_interrupt + 1 + MemoryManagement_interrupt + 1 + BusFault_interrupt + 1 + UsageFault_interrupt + 1);');
|
||||
end;
|
||||
end
|
||||
else
|
||||
|
||||
@ -350,7 +350,7 @@ CPU_SPECIFIC_COMMON_UNITS=
|
||||
ifeq ($(ARCH),arm)
|
||||
CPU_SPECIFIC_COMMON_UNITS=sysutils sysconst
|
||||
ifeq ($(SUBARCH),armv7m)
|
||||
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc13xx lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn stm32f10x_cl lpc13xx lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
endif
|
||||
ifeq ($(SUBARCH),armv7em)
|
||||
CPU_UNITS=lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
@ -362,7 +362,7 @@ ifeq ($(SUBARCH),armv4)
|
||||
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
|
||||
endif
|
||||
ifeq ($(SUBARCH),armv6m)
|
||||
CPU_UNITS=lpc8xx lpc11xx lpc122x cortexm0
|
||||
CPU_UNITS=lpc8xx lpc11xx lpc122x stm32f0xx cortexm0
|
||||
endif
|
||||
endif
|
||||
ifeq ($(ARCH),avr)
|
||||
|
||||
@ -64,7 +64,7 @@ CPU_SPECIFIC_COMMON_UNITS=
|
||||
ifeq ($(ARCH),arm)
|
||||
CPU_SPECIFIC_COMMON_UNITS=sysutils sysconst
|
||||
ifeq ($(SUBARCH),armv7m)
|
||||
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc13xx lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn stm32f10x_cl lpc13xx lpc1768 lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
endif
|
||||
ifeq ($(SUBARCH),armv7em)
|
||||
CPU_UNITS=lm4f120 xmc4500 cortexm3 cortexm4 # thumb2_bare
|
||||
@ -76,7 +76,7 @@ ifeq ($(SUBARCH),armv4)
|
||||
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
|
||||
endif
|
||||
ifeq ($(SUBARCH),armv6m)
|
||||
CPU_UNITS=lpc8xx lpc11xx lpc122x cortexm0
|
||||
CPU_UNITS=lpc8xx lpc11xx lpc122x stm32f0xx cortexm0
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
@ -48,7 +48,7 @@ const
|
||||
|
||||
type
|
||||
{ ------------- System Control (SYSCON) ------------- }
|
||||
TSYSCONRegisters = record
|
||||
TSYSCON_Registers = record
|
||||
SYSMEMREMAP : longword;
|
||||
PRESETCTRL : longword;
|
||||
SYSPLLCTRL : longword;
|
||||
@ -106,7 +106,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Pin Connect Block (IOCON) ------------- }
|
||||
TIOCONRegisters = record
|
||||
TIOCON_Registers = record
|
||||
PIO2_6 : longword;
|
||||
RESERVED0 : longword;
|
||||
PIO2_0 : longword;
|
||||
@ -158,7 +158,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Power Management Unit (PMU) ------------- }
|
||||
TPMURegisters = record
|
||||
TPMU_Registers = record
|
||||
PCON : longword;
|
||||
GPREG0: longword;
|
||||
GPREG1: longword;
|
||||
@ -168,7 +168,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Flash Controller (FLASHCTRL) ------------- }
|
||||
TFLASHCTRLRegisters = record
|
||||
TFLASHCTRL_Registers = record
|
||||
RESERVED0: array [0 .. 3] of longword;
|
||||
FLASHCFG : longword;
|
||||
RESERVED1: array [0 .. 2] of longword;
|
||||
@ -186,7 +186,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- General Purpose Input/Output (GPIO) ------------- }
|
||||
TGPIORegisters = record
|
||||
TGPIO_Registers = record
|
||||
MASKED_ACCESS: array [0 .. 4095] of longword;
|
||||
RESERVED1 : array [0 .. 4095] of longword;
|
||||
DIR : longword;
|
||||
@ -200,7 +200,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Timer (TMR) ------------- }
|
||||
TTMRRegisters = record
|
||||
TTMR_Registers = record
|
||||
IR : longword;
|
||||
TCR : longword;
|
||||
TC : longword;
|
||||
@ -222,7 +222,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Asynchronous Receiver Transmitter (UART) ------------- }
|
||||
TUARTRegisters = record
|
||||
TUART_Registers = record
|
||||
RBR_THR_DLL: longword;
|
||||
DLM_IER : longword;
|
||||
IIR_FCR : longword;
|
||||
@ -244,7 +244,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Synchronous Serial Communication (SSP) ------------- }
|
||||
TSSPRegisters = record
|
||||
TSSP_Registers = record
|
||||
CR0 : longword;
|
||||
CR1 : longword;
|
||||
DR : longword;
|
||||
@ -257,7 +257,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Inter-Integrated Circuit (I2C) ------------- }
|
||||
TI2CRegisters = record
|
||||
TI2C_Registers = record
|
||||
CONSET : longword;
|
||||
STAT : longword;
|
||||
DAT : longword;
|
||||
@ -277,7 +277,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Watchdog Timer (WDT) ------------- }
|
||||
TWDTRegisters = record
|
||||
TWDT_Registers = record
|
||||
_MOD : longword;
|
||||
TC : longword;
|
||||
FEED : longword;
|
||||
@ -288,7 +288,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Analog-to-Digital Converter (ADC) ------------- }
|
||||
TADCRegisters = record
|
||||
TADC_Registers = record
|
||||
CR : longword;
|
||||
GDR : longword;
|
||||
RESERVED0: longword;
|
||||
@ -298,7 +298,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- CAN Controller (CAN) ------------- }
|
||||
TCANRegisters = record
|
||||
TCAN_Registers = record
|
||||
CNTL : longword;
|
||||
STAT : longword;
|
||||
EC : longword;
|
||||
@ -386,31 +386,32 @@ const
|
||||
{$ALIGN 2}
|
||||
|
||||
var
|
||||
LPC_I2C : TI2CRegisters absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDTRegisters absolute(LPC_WDT_BASE);
|
||||
LPC_UART : TUARTRegisters absolute(LPC_UART_BASE);
|
||||
LPC_TMR16B0 : TTMRRegisters absolute(LPC_CT16B0_BASE);
|
||||
LPC_TMR16B1 : TTMRRegisters absolute(LPC_CT16B1_BASE);
|
||||
LPC_TMR32B0 : TTMRRegisters absolute(LPC_CT32B0_BASE);
|
||||
LPC_TMR32B1 : TTMRRegisters absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADCRegisters absolute(LPC_ADC_BASE);
|
||||
LPC_PMU : TPMURegisters absolute(LPC_PMU_BASE);
|
||||
LPC_FLASHCTRL: TPMURegisters absolute(LPC_PMU_BASE);
|
||||
LPC_SSP0 : TSSPRegisters absolute(LPC_SSP0_BASE);
|
||||
LPC_SSP1 : TSSPRegisters absolute(LPC_SSP1_BASE);
|
||||
LPC_CAN : TCANRegisters absolute(LPC_CAN_BASE);
|
||||
LPC_IOCON : TIOCONRegisters absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCONRegisters absolute(LPC_SYSCON_BASE);
|
||||
LPC_I2C : TI2C_Registers absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDT_Registers absolute(LPC_WDT_BASE);
|
||||
LPC_UART : TUART_Registers absolute(LPC_UART_BASE);
|
||||
LPC_TMR16B0 : TTMR_Registers absolute(LPC_CT16B0_BASE);
|
||||
LPC_TMR16B1 : TTMR_Registers absolute(LPC_CT16B1_BASE);
|
||||
LPC_TMR32B0 : TTMR_Registers absolute(LPC_CT32B0_BASE);
|
||||
LPC_TMR32B1 : TTMR_Registers absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADC_Registers absolute(LPC_ADC_BASE);
|
||||
LPC_PMU : TPMU_Registers absolute(LPC_PMU_BASE);
|
||||
LPC_FLASHCTRL: TPMU_Registers absolute(LPC_PMU_BASE);
|
||||
LPC_SSP0 : TSSP_Registers absolute(LPC_SSP0_BASE);
|
||||
LPC_SSP1 : TSSP_Registers absolute(LPC_SSP1_BASE);
|
||||
LPC_CAN : TCAN_Registers absolute(LPC_CAN_BASE);
|
||||
LPC_IOCON : TIOCON_Registers absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCON_Registers absolute(LPC_SYSCON_BASE);
|
||||
|
||||
LPC_GPIO0 : TGPIORegisters absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIORegisters absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIORegisters absolute(LPC_GPIO2_BASE);
|
||||
LPC_GPIO3 : TGPIORegisters absolute(LPC_GPIO3_BASE);
|
||||
LPC_GPIO0 : TGPIO_Registers absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIO_Registers absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIO_Registers absolute(LPC_GPIO2_BASE);
|
||||
LPC_GPIO3 : TGPIO_Registers absolute(LPC_GPIO3_BASE);
|
||||
|
||||
implementation
|
||||
|
||||
procedure NonMaskableInt_interrupt; external name 'NMI_interrupt';
|
||||
procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
|
||||
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
|
||||
procedure Startup_Checksum; external name 'Startup_Checksum';
|
||||
procedure SVCall_interrupt; external name 'SVCall_interrupt';
|
||||
procedure PendSV_interrupt; external name 'PendSV_interrupt';
|
||||
procedure SysTick_interrupt; external name 'SysTick_interrupt';
|
||||
@ -461,7 +462,7 @@ asm
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long Startup_Checksum
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
@ -506,6 +507,7 @@ asm
|
||||
|
||||
.weak NonMaskableInt_interrupt
|
||||
.weak Hardfault_interrupt
|
||||
.weak Startup_Checksum
|
||||
.weak SVCall_interrupt
|
||||
.weak PendSV_interrupt
|
||||
.weak SysTick_interrupt
|
||||
|
||||
@ -48,7 +48,7 @@ const
|
||||
|
||||
type
|
||||
{ ------------- Inter-Integrated Circuit (I2C) ------------- }
|
||||
TI2CRegisters = record
|
||||
TI2C_Registers = record
|
||||
CONSET : longword;
|
||||
STAT : longword;
|
||||
DAT : longword;
|
||||
@ -68,7 +68,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Watchdog Timer (WDT) ------------- }
|
||||
TWDTRegisters = record
|
||||
TWDT_Registers = record
|
||||
_MOD : longword;
|
||||
TC : longword;
|
||||
FEED : longword;
|
||||
@ -79,7 +79,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Asynchronous Receiver Transmitter 0 (UART0) ------------- }
|
||||
TUART0Registers = record
|
||||
TUART0_Registers = record
|
||||
DLL_THR_RBR : longword;
|
||||
IER_DLM : longword;
|
||||
FCR_IIR : longword;
|
||||
@ -101,7 +101,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Asynchronous Receiver Transmitter 1 (UART1) ------------- }
|
||||
TUART1Registers = record
|
||||
TUART1_Registers = record
|
||||
DLL_THR_RBR: longword;
|
||||
IER_DLM : longword;
|
||||
FCR_IIR : longword;
|
||||
@ -120,7 +120,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Timer (TCTxxBx) ------------- }
|
||||
TCTxxBxRegisters = record
|
||||
TCTxxBx_Registers = record
|
||||
IR : longword;
|
||||
TCR : longword;
|
||||
TC : longword;
|
||||
@ -142,7 +142,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Analog-to-Digital Converter (ADC) ------------- }
|
||||
TADCRegisters = record
|
||||
TADC_Registers = record
|
||||
CR : longword;
|
||||
GDR : longword;
|
||||
RESERVED0: longword;
|
||||
@ -152,7 +152,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Power Management Unit (PMU) ------------- }
|
||||
TPMURegisters = record
|
||||
TPMU_Registers = record
|
||||
PCON : longword;
|
||||
GPREG0: longword;
|
||||
GPREG1: longword;
|
||||
@ -162,7 +162,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Synchronous Serial Communication (SSP) ------------- }
|
||||
TSSPRegisters = record
|
||||
TSSP_Registers = record
|
||||
CR0 : longword;
|
||||
CR1 : longword;
|
||||
DR : longword;
|
||||
@ -176,7 +176,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Pin Connect Block (IOCON) ------------- }
|
||||
TIOCONRegisters = record
|
||||
TIOCON_Registers = record
|
||||
RESERVED0 : array [0 .. 1] of longword;
|
||||
PIO0_19 : longword;
|
||||
PIO0_20 : longword;
|
||||
@ -238,7 +238,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- System Control (SYSCON) ------------- }
|
||||
TSYSCONRegisters = record
|
||||
TSYSCON_Registers = record
|
||||
SYSMEMREMAP : longword;
|
||||
PRESETCTRL : longword;
|
||||
SYSPLLCTRL : longword;
|
||||
@ -302,7 +302,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Micro DMA Controller (MICRO_DMA) ------------- }
|
||||
TMICRODMARegisters = record
|
||||
TMICRODMA_Registers = record
|
||||
DMA_STATUS : longword;
|
||||
DMA_CFG : longword;
|
||||
CTRL_BASE_PTR : longword;
|
||||
@ -328,7 +328,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Real Time Clock (RTC) ------------- }
|
||||
TRTCRegisters = record
|
||||
TRTC_Registers = record
|
||||
DR : longword;
|
||||
MR : longword;
|
||||
LR : longword;
|
||||
@ -340,13 +340,13 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Analog Comparator (ACOMP) ------------- }
|
||||
TACOMPRegisters = record
|
||||
TACOMP_Registers = record
|
||||
CMP : longword;
|
||||
VLAD: longword;
|
||||
end;
|
||||
|
||||
{ ------------- General Purpose Input/Output (GPIO) ------------- }
|
||||
TGPIORegisters = record
|
||||
TGPIO_Registers = record
|
||||
MASK : longword;
|
||||
PIN : longword;
|
||||
_OUT : longword;
|
||||
@ -364,13 +364,13 @@ type
|
||||
IC : longword;
|
||||
end;
|
||||
|
||||
TFLASHCTRLRegisters = record
|
||||
TFLASHCTRL_Registers = record
|
||||
RESERVED0: array [0 .. 9] of longword;
|
||||
FLASHCFG : longword;
|
||||
end;
|
||||
|
||||
{ ------------- CRC Engine(CRC) ------------- }
|
||||
TCRCRegisters = record
|
||||
TCRC_Registers = record
|
||||
MODE: longword;
|
||||
SEED: longword;
|
||||
SUM : longword;
|
||||
@ -420,33 +420,34 @@ const
|
||||
{$ALIGN 2}
|
||||
|
||||
var
|
||||
LPC_I2C : TI2CRegisters absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDTRegisters absolute(LPC_WDT_BASE);
|
||||
LPC_UART0 : TUART0Registers absolute(LPC_UART0_BASE);
|
||||
LPC_UART1 : TUART1Registers absolute(LPC_UART1_BASE);
|
||||
LPC_CT16B0 : TCTxxBxRegisters absolute(LPC_CT16B0_BASE);
|
||||
LPC_CT16B1 : TCTxxBxRegisters absolute(LPC_CT16B1_BASE);
|
||||
LPC_CT32B0 : TCTxxBxRegisters absolute(LPC_CT32B0_BASE);
|
||||
LPC_CT23B1 : TCTxxBxRegisters absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADCRegisters absolute(LPC_ADC_BASE);
|
||||
LPC_PMU : TPMURegisters absolute(LPC_PMU_BASE);
|
||||
LPC_SSP : TSSPRegisters absolute(LPC_SSP_BASE);
|
||||
LPC_IOCON : TIOCONRegisters absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCONRegisters absolute(LPC_SYSCON_BASE);
|
||||
LPC_MICRO_DMA: TMICRODMARegisters absolute(LPC_MICRO_DMA_BASE);
|
||||
LPC_RTC : TRTCRegisters absolute(LPC_RTC_BASE);
|
||||
LPC_ACOMP : TACOMPRegisters absolute(LPC_ACOMP_BASE);
|
||||
LPC_I2C : TI2C_Registers absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDT_Registers absolute(LPC_WDT_BASE);
|
||||
LPC_UART0 : TUART0_Registers absolute(LPC_UART0_BASE);
|
||||
LPC_UART1 : TUART1_Registers absolute(LPC_UART1_BASE);
|
||||
LPC_CT16B0 : TCTxxBx_Registers absolute(LPC_CT16B0_BASE);
|
||||
LPC_CT16B1 : TCTxxBx_Registers absolute(LPC_CT16B1_BASE);
|
||||
LPC_CT32B0 : TCTxxBx_Registers absolute(LPC_CT32B0_BASE);
|
||||
LPC_CT23B1 : TCTxxBx_Registers absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADC_Registers absolute(LPC_ADC_BASE);
|
||||
LPC_PMU : TPMU_Registers absolute(LPC_PMU_BASE);
|
||||
LPC_SSP : TSSP_Registers absolute(LPC_SSP_BASE);
|
||||
LPC_IOCON : TIOCON_Registers absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCON_Registers absolute(LPC_SYSCON_BASE);
|
||||
LPC_MICRO_DMA: TMICRODMA_Registers absolute(LPC_MICRO_DMA_BASE);
|
||||
LPC_RTC : TRTC_Registers absolute(LPC_RTC_BASE);
|
||||
LPC_ACOMP : TACOMP_Registers absolute(LPC_ACOMP_BASE);
|
||||
|
||||
LPC_GPIO0 : TGPIORegisters absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIORegisters absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIORegisters absolute(LPC_GPIO2_BASE);
|
||||
LPC_FLASHCTRL: TFLASHCTRLRegisters absolute(LPC_FLASHCTRL_BASE);
|
||||
LPC_CRC : TCRCRegisters absolute(LPC_CRC_BASE);
|
||||
LPC_GPIO0 : TGPIO_Registers absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIO_Registers absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIO_Registers absolute(LPC_GPIO2_BASE);
|
||||
LPC_FLASHCTRL: TFLASHCTRL_Registers absolute(LPC_FLASHCTRL_BASE);
|
||||
LPC_CRC : TCRC_Registers absolute(LPC_CRC_BASE);
|
||||
|
||||
implementation
|
||||
|
||||
procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
|
||||
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
|
||||
procedure Startup_Checksum; external name 'Startup_Checksum';
|
||||
procedure SVCall_interrupt; external name 'SVCall_interrupt';
|
||||
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
|
||||
procedure PendSV_interrupt; external name 'PendSV_interrupt';
|
||||
@ -497,7 +498,7 @@ asm
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long Startup_Checksum
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
@ -542,6 +543,7 @@ asm
|
||||
|
||||
.weak NonMaskableInt_interrupt
|
||||
.weak Hardfault_interrupt
|
||||
.weak Startup_Checksum
|
||||
.weak SVCall_interrupt
|
||||
.weak DebugMonitor_interrupt
|
||||
.weak PendSV_interrupt
|
||||
|
||||
@ -81,7 +81,7 @@ const
|
||||
{ ------------- System Control (SYSCON) ------------- }
|
||||
|
||||
type
|
||||
TSYSCONRegisters = record
|
||||
TSYSCON_Registers = record
|
||||
SYSMEMREMAP : longword;
|
||||
PRESETCTRL : longword;
|
||||
SYSPLLCTRL : longword;
|
||||
@ -150,7 +150,7 @@ type
|
||||
|
||||
{ ------------- Pin Connect Block (IOCON) ------------- }
|
||||
|
||||
TIOCONRegisters = record
|
||||
TIOCON_Registers = record
|
||||
PIO2_6 : longword;
|
||||
RESERVED0 : longword;
|
||||
PIO2_0 : longword;
|
||||
@ -202,7 +202,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Power Management Unit (PMU) ------------- }
|
||||
TPMURegisters = record
|
||||
TPMU_Registers = record
|
||||
PCON : longword;
|
||||
GPREG0: longword;
|
||||
GPREG1: longword;
|
||||
@ -211,7 +211,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- General Purpose Input/Output (GPIO) ------------- }
|
||||
TGPIORegisters = record
|
||||
TGPIO_Registers = record
|
||||
MASKED_ACCESS: array [0 .. 4095] of longword;
|
||||
RESERVED1 : array [0 .. 4095] of longword;
|
||||
DIR : longword;
|
||||
@ -225,7 +225,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Timer (TMR) ------------- }
|
||||
TTMRRegisters = record
|
||||
TTMR_Registers = record
|
||||
IR : longword;
|
||||
TCR : longword;
|
||||
TC : longword;
|
||||
@ -246,7 +246,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Asynchronous Receiver Transmitter (UART) ------------- }
|
||||
TUARTRegisters = record
|
||||
TUART_Registers = record
|
||||
DLL : longword;
|
||||
DLM : longword;
|
||||
FCR : longword;
|
||||
@ -268,7 +268,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Synchronous Serial Communication (SSP) ------------- }
|
||||
TSSPRegisters = record
|
||||
TSSP_Registers = record
|
||||
CR0 : longword;
|
||||
CR1 : longword;
|
||||
DR : longword;
|
||||
@ -281,7 +281,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Inter-Integrated Circuit (I2C) ------------- }
|
||||
TI2CRegisters = record
|
||||
TI2C_Registers = record
|
||||
CONSET : longword;
|
||||
STAT : longword;
|
||||
DAT : longword;
|
||||
@ -302,7 +302,7 @@ type
|
||||
|
||||
{ ------------- Watchdog Timer (WDT) ------------- }
|
||||
|
||||
TWDTRegisters = record
|
||||
TWDT_Registers = record
|
||||
_MOD : longword;
|
||||
TC : longword;
|
||||
FEED : longword;
|
||||
@ -313,7 +313,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Analog-to-Digital Converter (ADC) ------------- }
|
||||
TADCRegisters = record
|
||||
TADC_Registers = record
|
||||
CR : longword;
|
||||
GDR : longword;
|
||||
RESERVED0: longword;
|
||||
@ -323,7 +323,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Serial Bus (USB) ------------- }
|
||||
TUSBRegisters = record
|
||||
TUSB_Registers = record
|
||||
DevIntSt : longword;
|
||||
DevIntEn : longword;
|
||||
DevIntClr: longword;
|
||||
@ -375,25 +375,25 @@ const
|
||||
{ **************************************************************************** }
|
||||
|
||||
var
|
||||
LPC_I2C : TI2CRegisters absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDTRegisters absolute(LPC_WDT_BASE);
|
||||
LPC_UART : TUARTRegisters absolute(LPC_UART_BASE);
|
||||
LPC_CT16B0 : TTMRRegisters absolute(LPC_CT16B0_BASE);
|
||||
LPC_CT16B1 : TTMRRegisters absolute(LPC_CT16B1_BASE);
|
||||
LPC_CT32B0 : TTMRRegisters absolute(LPC_CT32B0_BASE);
|
||||
LPC_CT23B1 : TTMRRegisters absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADCRegisters absolute(LPC_ADC_BASE);
|
||||
LPC_USB : TUSBRegisters absolute(LPC_USB_BASE);
|
||||
LPC_PMU : TPMURegisters absolute(LPC_PMU_BASE);
|
||||
LPC_SSP0 : TSSPRegisters absolute(LPC_SSP0_BASE);
|
||||
LPC_IOCON : TIOCONRegisters absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCONRegisters absolute(LPC_SYSCON_BASE);
|
||||
LPC_SSP1 : TSSPRegisters absolute(LPC_SSP0_BASE);
|
||||
LPC_I2C : TI2C_Registers absolute(LPC_I2C_BASE);
|
||||
LPC_WDT : TWDT_Registers absolute(LPC_WDT_BASE);
|
||||
LPC_UART : TUART_Registers absolute(LPC_UART_BASE);
|
||||
LPC_CT16B0 : TTMR_Registers absolute(LPC_CT16B0_BASE);
|
||||
LPC_CT16B1 : TTMR_Registers absolute(LPC_CT16B1_BASE);
|
||||
LPC_CT32B0 : TTMR_Registers absolute(LPC_CT32B0_BASE);
|
||||
LPC_CT23B1 : TTMR_Registers absolute(LPC_CT32B1_BASE);
|
||||
LPC_ADC : TADC_Registers absolute(LPC_ADC_BASE);
|
||||
LPC_USB : TUSB_Registers absolute(LPC_USB_BASE);
|
||||
LPC_PMU : TPMU_Registers absolute(LPC_PMU_BASE);
|
||||
LPC_SSP0 : TSSP_Registers absolute(LPC_SSP0_BASE);
|
||||
LPC_IOCON : TIOCON_Registers absolute(LPC_IOCON_BASE);
|
||||
LPC_SYSCON : TSYSCON_Registers absolute(LPC_SYSCON_BASE);
|
||||
LPC_SSP1 : TSSP_Registers absolute(LPC_SSP0_BASE);
|
||||
|
||||
LPC_GPIO0 : TGPIORegisters absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIORegisters absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIORegisters absolute(LPC_GPIO2_BASE);
|
||||
LPC_GPIO3 : TGPIORegisters absolute(LPC_GPIO3_BASE);
|
||||
LPC_GPIO0 : TGPIO_Registers absolute(LPC_GPIO0_BASE);
|
||||
LPC_GPIO1 : TGPIO_Registers absolute(LPC_GPIO1_BASE);
|
||||
LPC_GPIO2 : TGPIO_Registers absolute(LPC_GPIO2_BASE);
|
||||
LPC_GPIO3 : TGPIO_Registers absolute(LPC_GPIO3_BASE);
|
||||
|
||||
implementation
|
||||
|
||||
@ -401,6 +401,7 @@ procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
|
||||
procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
|
||||
procedure BusFault_interrupt; external name 'BusFault_interrupt';
|
||||
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
|
||||
procedure Startup_Checksum; external name 'Startup_Checksum';
|
||||
procedure SVCall_interrupt; external name 'SVCall_interrupt';
|
||||
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
|
||||
procedure PendSV_interrupt; external name 'PendSV_interrupt';
|
||||
@ -464,7 +465,7 @@ procedure EINT1_Interrupt; external name 'EINT1_Interrupt';
|
||||
procedure EINT0_Interrupt; external name 'EINT0_Interrupt';
|
||||
procedure SSP1_Interrupt; external name 'SSP1_Interrupt';
|
||||
|
||||
{$I cortexm0_start.inc}
|
||||
{$I cortexm3_start.inc}
|
||||
|
||||
procedure Vectors; assembler;
|
||||
nostackframe;
|
||||
@ -479,7 +480,7 @@ asm
|
||||
.long MemoryManagement_interrupt
|
||||
.long BusFault_interrupt
|
||||
.long UsageFault_interrupt
|
||||
.long 0
|
||||
.long Startup_Checksum
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
@ -552,6 +553,7 @@ asm
|
||||
.weak MemoryManagement_interrupt
|
||||
.weak BusFault_interrupt
|
||||
.weak UsageFault_interrupt
|
||||
.weak Startup_Checksum
|
||||
.weak SVCall_interrupt
|
||||
.weak DebugMonitor_interrupt
|
||||
.weak PendSV_interrupt
|
||||
|
||||
@ -38,7 +38,7 @@ const
|
||||
|
||||
type
|
||||
{ ------------- System Control (SYSCON) ------------- }
|
||||
TSYSCONRegisters = record
|
||||
TSYSCON_Registers = record
|
||||
SYSMEMREMAP : longword;
|
||||
PRESETCTRL : longword;
|
||||
SYSPLLCTRL : longword;
|
||||
@ -90,7 +90,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Pin Connect Block (IOCON) ------------- }
|
||||
TIOCONRegisters = record
|
||||
TIOCON_Registers = record
|
||||
PIO0_17 : longword;
|
||||
PIO0_13 : longword;
|
||||
PIO0_12 : longword;
|
||||
@ -113,7 +113,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Flash Controller (FLASHCTRL) ------------- }
|
||||
TFLASHCTRLRegisters = record
|
||||
TFLASHCTRL_Registers = record
|
||||
RESERVED0: array [0 .. 3] of longword;
|
||||
FLASHCFG : longword;
|
||||
RESERVED1: array [0 .. 2] of longword;
|
||||
@ -124,7 +124,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Power Management Unit (PMU) ------------- }
|
||||
TPMURegisters = record
|
||||
TPMU_Registers = record
|
||||
PCON : longword;
|
||||
GPREG0 : longword;
|
||||
GPREG1 : longword;
|
||||
@ -134,14 +134,14 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Switch Matrix Register (SWM) ------------- }
|
||||
TSWMRegisters = record
|
||||
TSWM_Registers = record
|
||||
PINASSIGN : array [0 .. 8] of longword;
|
||||
RESERVED0 : array [0 .. 102] of longword;
|
||||
PINENABLE0: longword;
|
||||
end;
|
||||
|
||||
{ ------------- General Purpose Input/Output (GPIO) ------------- }
|
||||
TGPIOPORTRegisters = record
|
||||
TGPIOPORT_Registers = record
|
||||
B0 : array [0 .. 17] of byte;
|
||||
RESERVED0: array [0 .. 2038] of word;
|
||||
W0 : array [0 .. 17] of longword;
|
||||
@ -162,7 +162,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Pin interrupts/pattern match engine (PIN_INT) ------------- }
|
||||
TPININTRegisters = record
|
||||
TPININT_Registers = record
|
||||
ISEL : longword;
|
||||
IENR : longword;
|
||||
SIENR : longword;
|
||||
@ -179,20 +179,20 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- CRC Engine (CRC) ------------- }
|
||||
TCRCRegisters = record
|
||||
TCRC_Registers = record
|
||||
MODE: longword;
|
||||
SEED: longword;
|
||||
SUM : longword;
|
||||
end;
|
||||
|
||||
{ ------------- Comparator (CMP) ------------- }
|
||||
TCMPRegisters = record
|
||||
TCMP_Registers = record
|
||||
CTRL: longword;
|
||||
LAD : longword;
|
||||
end;
|
||||
|
||||
{ ------------- Wakeup Timer (WKT) ------------- }
|
||||
TWKTRegisters = record
|
||||
TWKT_Registers = record
|
||||
CTRL : longword;
|
||||
RESERVED0: array [0 .. 1] of longword;
|
||||
COUNT : longword;
|
||||
@ -206,7 +206,7 @@ type
|
||||
STAT : longword;
|
||||
end;
|
||||
|
||||
TMRTRegisters = record
|
||||
TMRT_Registers = record
|
||||
CHANNEL : array [0 .. 3] of TMRTChannel;
|
||||
RESERVED0: array [0 .. 0] of longword;
|
||||
IDLE_CH : longword;
|
||||
@ -214,7 +214,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Universal Asynchronous Receiver Transmitter (USART) ------------- }
|
||||
TUSARTRegisters = record
|
||||
TUSART_Registers = record
|
||||
CFG : longword;
|
||||
CTRL : longword;
|
||||
STAT : longword;
|
||||
@ -228,7 +228,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Synchronous Serial Interface Controller (SPI) ------------- }
|
||||
TSPIRegisters = record
|
||||
TSPI_Registers = record
|
||||
CFG : longword;
|
||||
DLY : longword;
|
||||
STAT : longword;
|
||||
@ -243,7 +243,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Inter-Integrated Circuit (I2C) ------------- }
|
||||
TI2CRegisters = record
|
||||
TI2C_Registers = record
|
||||
CFG : longword;
|
||||
STAT : longword;
|
||||
INTENSET : longword;
|
||||
@ -286,7 +286,7 @@ type
|
||||
end;
|
||||
|
||||
type
|
||||
TSCTRegisters = record
|
||||
TSCT_Registers = record
|
||||
CONFIG : longword;
|
||||
CTRL : longword;
|
||||
LIMIT : longword;
|
||||
@ -316,7 +316,7 @@ type
|
||||
end;
|
||||
|
||||
{ ------------- Watchdog Timer (WDT) ------------- }
|
||||
TWDTRegisters = record
|
||||
TWDT_Registers = record
|
||||
_MOD : longword;
|
||||
TC : longword;
|
||||
FEED : longword;
|
||||
@ -365,30 +365,31 @@ const
|
||||
{$ALIGN 2}
|
||||
|
||||
var
|
||||
WDT : TWDTRegisters absolute LPC_WDT_BASE;
|
||||
MRT : TMRTRegisters absolute LPC_MRT_BASE;
|
||||
WKT : TWKTRegisters absolute LPC_WKT_BASE;
|
||||
SWM : TSWMRegisters absolute LPC_SWM_BASE;
|
||||
PMU : TPMURegisters absolute LPC_PMU_BASE;
|
||||
CMP : TCMPRegisters absolute LPC_CMP_BASE;
|
||||
FLASHCTRL: TFLASHCTRLRegisters absolute LPC_FLASHCTRL_BASE;
|
||||
IOCON : TIOCONRegisters absolute LPC_IOCON_BASE;
|
||||
SYSCON : TSysConRegisters absolute LPC_SYSCON_BASE;
|
||||
I2C : TI2CRegisters absolute LPC_I2C_BASE;
|
||||
SPI0 : TSPIRegisters absolute LPC_SPI0_BASE;
|
||||
SPI1 : TSPIRegisters absolute LPC_SPI1_BASE;
|
||||
USART0 : TUSARTRegisters absolute LPC_USART0_BASE;
|
||||
USART1 : TUSARTRegisters absolute LPC_USART0_BASE;
|
||||
USART2 : TUSARTRegisters absolute LPC_USART0_BASE;
|
||||
CRC : TCRCRegisters absolute LPC_CRC_BASE;
|
||||
SCT : TSCTRegisters absolute LPC_SCT_BASE;
|
||||
GPIO_PORT: TGPIOPortRegisters absolute LPC_GPIO_PORT_BASE;
|
||||
PIN_INT : TPININTRegisters absolute LPC_PIN_INT_BASE;
|
||||
WDT : TWDT_Registers absolute LPC_WDT_BASE;
|
||||
MRT : TMRT_Registers absolute LPC_MRT_BASE;
|
||||
WKT : TWKT_Registers absolute LPC_WKT_BASE;
|
||||
SWM : TSWM_Registers absolute LPC_SWM_BASE;
|
||||
PMU : TPMU_Registers absolute LPC_PMU_BASE;
|
||||
CMP : TCMP_Registers absolute LPC_CMP_BASE;
|
||||
FLASHCTRL: TFLASHCTRL_Registers absolute LPC_FLASHCTRL_BASE;
|
||||
IOCON : TIOCON_Registers absolute LPC_IOCON_BASE;
|
||||
SYSCON : TSysCon_Registers absolute LPC_SYSCON_BASE;
|
||||
I2C : TI2C_Registers absolute LPC_I2C_BASE;
|
||||
SPI0 : TSPI_Registers absolute LPC_SPI0_BASE;
|
||||
SPI1 : TSPI_Registers absolute LPC_SPI1_BASE;
|
||||
USART0 : TUSART_Registers absolute LPC_USART0_BASE;
|
||||
USART1 : TUSART_Registers absolute LPC_USART0_BASE;
|
||||
USART2 : TUSART_Registers absolute LPC_USART0_BASE;
|
||||
CRC : TCRC_Registers absolute LPC_CRC_BASE;
|
||||
SCT : TSCT_Registers absolute LPC_SCT_BASE;
|
||||
GPIO_PORT: TGPIOPort_Registers absolute LPC_GPIO_PORT_BASE;
|
||||
PIN_INT : TPININT_Registers absolute LPC_PIN_INT_BASE;
|
||||
|
||||
implementation
|
||||
|
||||
procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
|
||||
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
|
||||
procedure Startup_Checksum; external name 'Startup_Checksum';
|
||||
procedure SVCall_interrupt; external name 'SVCall_interrupt';
|
||||
procedure PendSV_interrupt; external name 'PendSV_interrupt';
|
||||
procedure SysTick_interrupt; external name 'SysTick_interrupt';
|
||||
@ -429,7 +430,7 @@ asm
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long Startup_Checksum
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
@ -474,6 +475,7 @@ asm
|
||||
|
||||
.weak NonMaskableInt_interrupt
|
||||
.weak Hardfault_interrupt
|
||||
.weak Startup_Checksum
|
||||
.weak SVCall_interrupt
|
||||
.weak PendSV_interrupt
|
||||
.weak SysTick_interrupt
|
||||
|
||||
3177
rtl/embedded/arm/stm32f0xx.pp
Normal file
3177
rtl/embedded/arm/stm32f0xx.pp
Normal file
File diff suppressed because it is too large
Load Diff
3178
rtl/embedded/arm/stm32f10x_cl.pp
Normal file
3178
rtl/embedded/arm/stm32f10x_cl.pp
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user