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Fixes for aarch64.
Merged revision(s) 39948, 39951, 39953 from trunk: * Fixed interface delegation for aarch64 (tdel1 and tdel2 tests). It was broken by r31676 which did not take in account r29953. As a consequence $self was passed in register x1 instead of x0 when the method result is of a managed type. This fix enables changing order of the $self and $result parameters only for aarch64 AND llvm combination where it is actually needed. The issue with interface delegation still exists for aarch64-llvm and need to be fixed separately. Probably by applying llvm-specific workarounds as it was made in r29953 for regular aarch64 targets. ........ * Fixed bug #17413 (and the tw17413 test) for aarch64 by adding additional check. ........ * aarch64: Fixed loading of a function result which is returned in 4 32-bit MM registers to 2 64-bit int registers. Bug #30329. ........ git-svn-id: branches/fixes_3_2@40543 -
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yury
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2f08c63947
commit
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@ -1040,13 +1040,19 @@ implementation
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procedure tcgaarch64.a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize: tcgsize; mmreg, intreg: tregister; shuffle: pmmshuffle);
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var
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r : tregister;
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begin
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if not shufflescalar(shuffle) then
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internalerror(2014122802);
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if not(tcgsize2size[fromsize] in [4,8]) or
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(tcgsize2size[fromsize]<>tcgsize2size[tosize]) then
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(tcgsize2size[fromsize]>tcgsize2size[tosize]) then
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internalerror(2014122804);
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list.concat(taicpu.op_reg_reg(A_UMOV,intreg,mmreg));
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if tcgsize2size[fromsize]<tcgsize2size[tosize] then
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r:=makeregsize(intreg,fromsize)
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else
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r:=intreg;
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list.concat(taicpu.op_reg_reg(A_UMOV,r,mmreg));
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end;
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@ -112,7 +112,9 @@ implementation
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{ ... at the place we are looking for }
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references_equal(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.reference,rr^.old^) and
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{ its address cannot have escaped the current routine }
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not(tabstractvarsym(tloadnode(n).symtableentry).addr_taken) then
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not(tabstractvarsym(tloadnode(n).symtableentry).addr_taken) and
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{ it is not accessed in nested procedures }
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not(tabstractvarsym(tloadnode(n).symtableentry).different_scope) then
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begin
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{ relocate variable }
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tcgloadnode(n).changereflocation(rr^.new^);
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@ -704,11 +704,11 @@ implementation
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sizeleft : aint;
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tempref : treference;
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loadsize : tcgint;
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tempreg : tregister;
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{$ifdef mips}
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//tmpreg : tregister;
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{$endif mips}
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{$ifndef cpu64bitalu}
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tempreg : tregister;
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reg64 : tregister64;
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{$if defined(cpu8bitalu)}
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curparaloc : PCGParaLocation;
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@ -780,27 +780,68 @@ implementation
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begin
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if not assigned(paraloc^.next) then
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internalerror(200410104);
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc,vardef);
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{ reg->reg, alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reghi,8);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^.next^,destloc.register128.reglo,8);
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc,vardef);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reglo,8);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^.next^,destloc.register128.reghi,8);
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end;
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case tcgsize2size[paraloc^.size] of
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8:
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begin
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc,vardef);
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{ reg->reg, alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reghi,8);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^.next^,destloc.register128.reglo,8);
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc,vardef);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reglo,8);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^.next^,destloc.register128.reghi,8);
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end;
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end;
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4:
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begin
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{ The 128-bit parameter is located in 4 32-bit MM registers.
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It is needed to copy them to 2 64-bit int registers.
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A code generator or a target cpu must support loading of a 32-bit MM register to
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a 64-bit int register, zero extending it. }
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if target_info.endian=ENDIAN_BIG then
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internalerror(2018101702); // Big endian support not implemented yet
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gen_alloc_regloc(list,destloc,vardef);
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tempreg:=cg.getintregister(list,OS_64);
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// Low part of the 128-bit param
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unget_para(paraloc^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,tempreg,4);
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paraloc:=paraloc^.next;
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if paraloc=nil then
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internalerror(2018101703);
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unget_para(paraloc^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reglo,4);
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cg.a_op_const_reg(list,OP_SHL,OS_64,32,destloc.register128.reglo);
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cg.a_op_reg_reg(list,OP_OR,OS_64,tempreg,destloc.register128.reglo);
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// High part of the 128-bit param
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paraloc:=paraloc^.next;
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if paraloc=nil then
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internalerror(2018101704);
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unget_para(paraloc^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,tempreg,4);
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paraloc:=paraloc^.next;
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if paraloc=nil then
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internalerror(2018101705);
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unget_para(paraloc^);
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cg.a_load_cgparaloc_anyreg(list,OS_64,paraloc^,destloc.register128.reghi,4);
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cg.a_op_const_reg(list,OP_SHL,OS_64,32,destloc.register128.reghi);
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cg.a_op_reg_reg(list,OP_OR,OS_64,tempreg,destloc.register128.reghi);
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end
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else
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internalerror(2018101701);
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end;
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end;
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LOC_REFERENCE:
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begin
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@ -124,18 +124,17 @@ const
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paranr_blockselfpara = 1;
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paranr_parentfp = 2;
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paranr_parentfp_delphi_cc_leftright = 2;
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{$ifndef aarch64}
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paranr_self = 3;
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paranr_result = 4;
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{$else aarch64}
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{ on AArch64, the result parameter is passed in a special register, so its
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order doesn't really matter -- except for LLVM, where the "sret" parameter
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{$if defined(aarch64) and defined(llvm)}
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{ for AArch64 on LLVM, the "sret" parameter
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must always be the first -> give it a higher number; can't do it for other
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platforms, because that would change the register assignment/parameter order
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and the current one is presumably Delphi-compatible }
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paranr_result = 3;
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paranr_self = 4;
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{$endif aarch64}
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{$else}
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paranr_self = 3;
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paranr_result = 4;
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{$endif}
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paranr_vmt = 5;
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{ the implicit parameters for Objective-C methods need to come
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