mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 03:48:07 +02:00
o refactored some peephole optimizer code:
* updated TAOptObj.RegUsedAfterInstruction with the arm implementation and removed the arm specific implementation * RegLoadedWithNewValue and InstructionLoadsFromReg are now a methods of TAoptBase * moved RegEndOfLife to TAOptObj * during this refactoring, fixed also TCpuAsmOptimizer.RegLoadedWithNewValue for arm regarding post/preindexed memory references: those modify the register but do not load it with a new value in the sense of RegLoadedWithNewValue git-svn-id: trunk@33000 -
This commit is contained in:
florian
parent
273f88a54c
commit
1266491085
@ -95,6 +95,12 @@ unit aoptbase;
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{ returns true if reg is modified by any instruction between p1 and p2 }
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function RegModifiedBetween(reg: TRegister; p1, p2: tai): Boolean;
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{ returns true if reg is loaded with a new value by hp }
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function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean; Virtual;
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{ returns true if hp loads a value from reg }
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function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; Virtual;
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end;
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function labelCanBeSkipped(p: tai_label): boolean;
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@ -285,6 +291,20 @@ unit aoptbase;
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end;
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function TAoptBase.RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean;
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begin
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{ save approximation }
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Result:=true;
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end;
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function TAoptBase.InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean;
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begin
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{ save approximation }
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Result:=true;
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end;
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{ ******************* Processor dependent stuff *************************** }
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Function TAOptBase.RegMaxSize(Reg: TRegister): TRegister;
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@ -315,6 +315,10 @@ Unit AoptObj;
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{ reg used after p? }
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function RegUsedAfterInstruction(reg: Tregister; p: tai; var AllUsedRegs: TAllUsedRegs): Boolean;
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{ returns true if reg reaches it's end of life at p, this means it is either
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reloaded with a new value or it is deallocated afterwards }
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function RegEndOfLife(reg: TRegister;p: taicpu): boolean;
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{ traces sucessive jumps to their final destination and sets it, e.g.
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je l1 je l3
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<code> <code>
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@ -1117,15 +1121,25 @@ Unit AoptObj;
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End;
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function TAOptObj.RegUsedAfterInstruction(reg: Tregister; p: tai;
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var AllUsedRegs: TAllUsedRegs): Boolean;
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begin
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AllUsedRegs[getregtype(reg)].Update(tai(p.Next),true);
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RegUsedAfterInstruction :=
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(AllUsedRegs[getregtype(reg)].IsUsed(reg)); { optimization and
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(not(getNextInstruction(p,p)) or
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not(regLoadedWithNewValue(supreg,false,p))); }
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end;
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function TAOptObj.RegUsedAfterInstruction(reg: Tregister; p: tai;var AllUsedRegs: TAllUsedRegs): Boolean;
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begin
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AllUsedRegs[getregtype(reg)].Update(tai(p.Next),true);
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RegUsedAfterInstruction :=
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AllUsedRegs[getregtype(reg)].IsUsed(reg) and
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not(regLoadedWithNewValue(reg,p)) and
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(
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not(GetNextInstruction(p,p)) or
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InstructionLoadsFromReg(reg,p) or
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not(regLoadedWithNewValue(reg,p))
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);
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end;
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function TAOptObj.RegEndOfLife(reg : TRegister;p : taicpu) : boolean;
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begin
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Result:=assigned(FindRegDealloc(reg,tai(p.Next))) or
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RegLoadedWithNewValue(reg,p);
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end;
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function SkipLabels(hp: tai; var hp2: tai): boolean;
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@ -39,11 +39,7 @@ Type
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procedure PeepHoleOptPass2;override;
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Function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
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function RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string): boolean;
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function RegUsedAfterInstruction(reg: Tregister; p: tai;
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var AllUsedRegs: TAllUsedRegs): Boolean;
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{ returns true if reg reaches it's end of life at p, this means it is either
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reloaded with a new value or it is deallocated afterwards }
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function RegEndOfLife(reg: TRegister;p: taicpu): boolean;
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{ gets the next tai object after current that contains info relevant
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to the optimizer in p1 which used the given register or does a
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change in program flow.
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@ -55,6 +51,9 @@ Type
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{ outputs a debug message into the assembler file }
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procedure DebugMsg(const s: string; p: tai);
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function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
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function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
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protected
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function LookForPreindexedPattern(p: taicpu): boolean;
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function LookForPostindexedPattern(p: taicpu): boolean;
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@ -167,67 +166,6 @@ Implementation
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end;
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end;
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function regLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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begin
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p := taicpu(hp);
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regLoadedWithNewValue := false;
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if not ((assigned(hp)) and (hp.typ = ait_instruction)) then
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exit;
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case p.opcode of
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{ These operands do not write into a register at all }
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A_CMP, A_CMN, A_TST, A_TEQ, A_B, A_BL, A_BX, A_BLX, A_SWI, A_MSR, A_PLD:
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exit;
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{Take care of post/preincremented store and loads, they will change their base register}
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A_STR, A_LDR:
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begin
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regLoadedWithNewValue :=
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(taicpu(p).oper[1]^.typ=top_ref) and
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(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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(taicpu(p).oper[1]^.ref^.base = reg);
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{STR does not load into it's first register}
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if p.opcode = A_STR then exit;
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end;
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{ These four are writing into the first 2 register, UMLAL and SMLAL will also read from them }
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A_UMLAL, A_UMULL, A_SMLAL, A_SMULL:
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regLoadedWithNewValue :=
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(p.oper[1]^.typ = top_reg) and
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(p.oper[1]^.reg = reg);
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{Loads to oper2 from coprocessor}
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{
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MCR/MRC is currently not supported in FPC
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A_MRC:
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regLoadedWithNewValue :=
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(p.oper[2]^.typ = top_reg) and
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(p.oper[2]^.reg = reg);
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}
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{Loads to all register in the registerset}
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A_LDM:
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regLoadedWithNewValue := (getsupreg(reg) in p.oper[1]^.regset^);
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A_POP:
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regLoadedWithNewValue := (getsupreg(reg) in p.oper[0]^.regset^) or
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(reg=NR_STACK_POINTER_REG);
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end;
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if regLoadedWithNewValue then
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exit;
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case p.oper[0]^.typ of
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{This is the case}
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top_reg:
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regLoadedWithNewValue := (p.oper[0]^.reg = reg) or
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{ LDRD }
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(p.opcode=A_LDR) and (p.oppostfix=PF_D) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg));
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{LDM/STM might write a new value to their index register}
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top_ref:
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regLoadedWithNewValue :=
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(taicpu(p).oper[0]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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(taicpu(p).oper[0]^.ref^.base = reg);
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end;
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end;
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function AlignedToQWord(const ref : treference) : boolean;
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begin
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@ -249,44 +187,6 @@ Implementation
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end;
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function instructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
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var
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p: taicpu;
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i: longint;
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begin
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instructionLoadsFromReg := false;
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if not (assigned(hp) and (hp.typ = ait_instruction)) then
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exit;
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p:=taicpu(hp);
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i:=1;
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{For these instructions we have to start on oper[0]}
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if (p.opcode in [A_STR, A_LDM, A_STM, A_PLD,
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A_CMP, A_CMN, A_TST, A_TEQ,
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A_B, A_BL, A_BX, A_BLX,
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A_SMLAL, A_UMLAL]) then i:=0;
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while(i<p.ops) do
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begin
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case p.oper[I]^.typ of
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top_reg:
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instructionLoadsFromReg := (p.oper[I]^.reg = reg) or
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{ STRD }
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((i=0) and (p.opcode=A_STR) and (p.oppostfix=PF_D) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg)));
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top_regset:
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instructionLoadsFromReg := (getsupreg(reg) in p.oper[I]^.regset^);
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top_shifterop:
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instructionLoadsFromReg := p.oper[I]^.shifterop^.rs = reg;
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top_ref:
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instructionLoadsFromReg :=
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(p.oper[I]^.ref^.base = reg) or
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(p.oper[I]^.ref^.index = reg);
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end;
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if instructionLoadsFromReg then exit; {Bailout if we found something}
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Inc(I);
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end;
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end;
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function isValidConstLoadStoreOffset(const aoffset: longint; const pf: TOpPostfix) : boolean;
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begin
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if GenerateThumb2Code then
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@ -297,27 +197,112 @@ Implementation
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(abs(aoffset)<256);
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end;
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function TCpuAsmOptimizer.RegUsedAfterInstruction(reg: Tregister; p: tai;
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var AllUsedRegs: TAllUsedRegs): Boolean;
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function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
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var
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p: taicpu;
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i: longint;
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begin
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AllUsedRegs[getregtype(reg)].Update(tai(p.Next),true);
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RegUsedAfterInstruction :=
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AllUsedRegs[getregtype(reg)].IsUsed(reg) and
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not(regLoadedWithNewValue(reg,p)) and
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(
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not(GetNextInstruction(p,p)) or
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instructionLoadsFromReg(reg,p) or
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not(regLoadedWithNewValue(reg,p))
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);
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instructionLoadsFromReg := false;
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if not (assigned(hp) and (hp.typ = ait_instruction)) then
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exit;
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p:=taicpu(hp);
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i:=1;
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{For these instructions we have to start on oper[0]}
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if (p.opcode in [A_STR, A_LDM, A_STM, A_PLD,
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A_CMP, A_CMN, A_TST, A_TEQ,
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A_B, A_BL, A_BX, A_BLX,
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A_SMLAL, A_UMLAL]) then i:=0;
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while(i<p.ops) do
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begin
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case p.oper[I]^.typ of
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top_reg:
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instructionLoadsFromReg := (p.oper[I]^.reg = reg) or
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{ STRD }
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((i=0) and (p.opcode=A_STR) and (p.oppostfix=PF_D) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg)));
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top_regset:
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instructionLoadsFromReg := (getsupreg(reg) in p.oper[I]^.regset^);
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top_shifterop:
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instructionLoadsFromReg := p.oper[I]^.shifterop^.rs = reg;
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top_ref:
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instructionLoadsFromReg :=
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(p.oper[I]^.ref^.base = reg) or
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(p.oper[I]^.ref^.index = reg);
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end;
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if instructionLoadsFromReg then exit; {Bailout if we found something}
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Inc(I);
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end;
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end;
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function TCpuAsmOptimizer.RegEndOfLife(reg : TRegister;p : taicpu) : boolean;
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function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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begin
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Result:=assigned(FindRegDealloc(reg,tai(p.Next))) or
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RegLoadedWithNewValue(reg,p);
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p := taicpu(hp);
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Result := false;
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if not ((assigned(hp)) and (hp.typ = ait_instruction)) then
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exit;
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case p.opcode of
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{ These operands do not write into a register at all }
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A_CMP, A_CMN, A_TST, A_TEQ, A_B, A_BL, A_BX, A_BLX, A_SWI, A_MSR, A_PLD:
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exit;
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{Take care of post/preincremented store and loads, they will change their base register}
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A_STR, A_LDR:
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begin
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Result := false;
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{ actually, this does not apply here because post-/preindexed does not mean that a register
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is loaded with a new value, it is only modified
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(taicpu(p).oper[1]^.typ=top_ref) and
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(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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(taicpu(p).oper[1]^.ref^.base = reg);
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}
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{ STR does not load into it's first register }
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if p.opcode = A_STR then
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exit;
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end;
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{ These four are writing into the first 2 register, UMLAL and SMLAL will also read from them }
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A_UMLAL, A_UMULL, A_SMLAL, A_SMULL:
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Result :=
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(p.oper[1]^.typ = top_reg) and
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(p.oper[1]^.reg = reg);
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{Loads to oper2 from coprocessor}
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{
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MCR/MRC is currently not supported in FPC
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A_MRC:
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Result :=
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(p.oper[2]^.typ = top_reg) and
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(p.oper[2]^.reg = reg);
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}
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{Loads to all register in the registerset}
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A_LDM:
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Result := (getsupreg(reg) in p.oper[1]^.regset^);
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A_POP:
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Result := (getsupreg(reg) in p.oper[0]^.regset^) or
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(reg=NR_STACK_POINTER_REG);
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end;
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if Result then
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exit;
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case p.oper[0]^.typ of
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{This is the case}
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top_reg:
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Result := (p.oper[0]^.reg = reg) or
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{ LDRD }
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(p.opcode=A_LDR) and (p.oppostfix=PF_D) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg));
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{LDM/STM might write a new value to their index register}
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top_ref:
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Result :=
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(taicpu(p).oper[0]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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(taicpu(p).oper[0]^.ref^.base = reg);
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end;
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end;
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function TCpuAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
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Out Next: tai; reg: TRegister): Boolean;
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begin
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@ -42,6 +42,8 @@ unit aoptcpu;
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function TryRemoveMovBeforeStore(var p: tai; next: taicpu; const storeops: TAsmOpSet): boolean;
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2; override;
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function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
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function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
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End;
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Implementation
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@ -73,29 +75,6 @@ unit aoptcpu;
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end;
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function regLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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begin
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p:=taicpu(hp);
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result:=false;
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if not ((assigned(hp)) and (hp.typ=ait_instruction)) then
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exit;
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case p.opcode of
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{ These instructions do not write into a register at all }
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A_NOP,
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A_C_EQ_D,A_C_EQ_S,A_C_LE_D,A_C_LE_S,A_C_LT_D,A_C_LT_S,
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A_BA,A_BC,
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A_SB,A_SH,A_SW,A_SWL,A_SWR,A_SWC1,A_SDC1:
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exit;
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end;
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result:=(p.ops>0) and (p.oper[0]^.typ=top_reg) and
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(p.oper[0]^.reg=reg);
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end;
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function CanBeCMOV(p: tai; condreg: tregister): boolean;
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begin
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result:=assigned(p) and (p.typ=ait_instruction) and
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@ -151,7 +130,7 @@ unit aoptcpu;
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end;
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function instructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
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function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
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var
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p: taicpu;
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i: longint;
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@ -178,6 +157,29 @@ unit aoptcpu;
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end;
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function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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begin
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p:=taicpu(hp);
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result:=false;
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if not ((assigned(hp)) and (hp.typ=ait_instruction)) then
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exit;
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case p.opcode of
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{ These instructions do not write into a register at all }
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A_NOP,
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A_C_EQ_D,A_C_EQ_S,A_C_LE_D,A_C_LE_S,A_C_LT_D,A_C_LT_S,
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A_BA,A_BC,
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A_SB,A_SH,A_SW,A_SWL,A_SWR,A_SWC1,A_SDC1:
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exit;
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end;
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result:=(p.ops>0) and (p.oper[0]^.typ=top_reg) and
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(p.oper[0]^.reg=reg);
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end;
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function TCpuAsmOptimizer.RegModifiedByInstruction(Reg: TRegister; p1: tai): boolean;
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var
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i : Longint;
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@ -38,6 +38,8 @@ unit aoptcpu;
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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||||
function RegUsedAfterInstruction(reg: Tregister; p: tai;
|
||||
var AllUsedRegs: TAllUsedRegs): Boolean;
|
||||
function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
|
||||
function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
|
||||
End;
|
||||
|
||||
Implementation
|
||||
@ -69,30 +71,7 @@ unit aoptcpu;
|
||||
end;
|
||||
|
||||
|
||||
function regLoadedWithNewValue(reg: tregister; hp: tai): boolean;
|
||||
var
|
||||
p: taicpu;
|
||||
begin
|
||||
p:=taicpu(hp);
|
||||
result:=false;
|
||||
if not ((assigned(hp)) and (hp.typ=ait_instruction)) then
|
||||
exit;
|
||||
|
||||
case p.opcode of
|
||||
{ These instructions do not write into a register at all }
|
||||
A_NOP,
|
||||
A_FCMPs,A_FCMPd,A_FCMPq,A_CMP,
|
||||
A_BA,A_Bxx,A_FBA,A_FBxx,
|
||||
A_STB,A_STH,A_ST,A_STF,A_STDF:
|
||||
exit;
|
||||
end;
|
||||
|
||||
result:=(p.ops>0) and (p.oper[p.ops-1]^.typ=top_reg) and
|
||||
(p.oper[p.ops-1]^.reg=reg);
|
||||
end;
|
||||
|
||||
|
||||
function instructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
|
||||
function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
|
||||
var
|
||||
p: taicpu;
|
||||
i: longint;
|
||||
@ -119,6 +98,29 @@ unit aoptcpu;
|
||||
end;
|
||||
|
||||
|
||||
function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
|
||||
var
|
||||
p: taicpu;
|
||||
begin
|
||||
p:=taicpu(hp);
|
||||
result:=false;
|
||||
if not ((assigned(hp)) and (hp.typ=ait_instruction)) then
|
||||
exit;
|
||||
|
||||
case p.opcode of
|
||||
{ These instructions do not write into a register at all }
|
||||
A_NOP,
|
||||
A_FCMPs,A_FCMPd,A_FCMPq,A_CMP,
|
||||
A_BA,A_Bxx,A_FBA,A_FBxx,
|
||||
A_STB,A_STH,A_ST,A_STF,A_STDF:
|
||||
exit;
|
||||
end;
|
||||
|
||||
result:=(p.ops>0) and (p.oper[p.ops-1]^.typ=top_reg) and
|
||||
(p.oper[p.ops-1]^.reg=reg);
|
||||
end;
|
||||
|
||||
|
||||
function TCpuAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
|
||||
var Next: tai; reg: TRegister): Boolean;
|
||||
begin
|
||||
|
||||
Loading…
Reference in New Issue
Block a user