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* arm assembler instructions can have 4 operands

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* qword comparisations fixed
This commit is contained in:
florian 2004-03-23 21:03:50 +00:00
parent ddb6d0d595
commit 1280635cc4
2 changed files with 13 additions and 5 deletions
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8
compiler/arm/cpubase.pas
View File

@ -314,7 +314,7 @@ unit cpubase;
*****************************************************************************}
const
max_operands = 3;
max_operands = 4;
{# Constant defining possibly all registers which might require saving }
ALL_OTHERREGISTERS = [];
@ -570,7 +570,11 @@ unit cpubase;
end.
{
$Log$
Revision 1.28 2004-03-13 18:45:40 florian
Revision 1.29 2004-03-23 21:03:50 florian
* arm assembler instructions can have 4 operands
* qword comparisations fixed
Revision 1.28 2004/03/13 18:45:40 florian
* floating compares fixed
* unary minus for floats fixed

10
compiler/arm/narmadd.pas
View File

@ -261,8 +261,8 @@ interface
{ operation requiring proper N, Z and C flags ? }
if unsigned or (nodetype in [equaln,unequaln]) then
begin
exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
exprasmlist.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi),C_EQ));
exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi));
exprasmlist.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo),C_EQ));
end
{ operation requiring proper N, V and C flags ? }
else if nodetype in [gten,ltn] then
@ -343,7 +343,11 @@ begin
end.
{
$Log$
Revision 1.13 2004-03-13 18:45:40 florian
Revision 1.14 2004-03-23 21:03:50 florian
* arm assembler instructions can have 4 operands
* qword comparisations fixed
Revision 1.13 2004/03/13 18:45:40 florian
* floating compares fixed
* unary minus for floats fixed