From 14bb0a51b4d4af76d6cef6da59b60f3c6997db87 Mon Sep 17 00:00:00 2001 From: mazen Date: Wed, 2 Oct 2002 22:20:28 +0000 Subject: [PATCH] + out registers allocator for the first 6 scalar parameters which must be passed into %o0..%o5 --- compiler/sparc/aasmcpu.pas | 56 ++++++++-------- compiler/sparc/cgcpu.pas | 125 +++++++++++++++++++++-------------- compiler/sparc/cpubase.pas | 6 +- compiler/sparc/cpugas.pas | 10 +-- compiler/sparc/registers.inc | 11 ++- 5 files changed, 123 insertions(+), 85 deletions(-) diff --git a/compiler/sparc/aasmcpu.pas b/compiler/sparc/aasmcpu.pas index b426d7c0e0..74742fe676 100644 --- a/compiler/sparc/aasmcpu.pas +++ b/compiler/sparc/aasmcpu.pas @@ -131,14 +131,14 @@ uses constructor tai_align.create(b: byte); begin inherited create(b); - reg := R_NO; + reg := R_NONE; end; constructor tai_align.create_op(b: byte; _op: byte); begin inherited create_op(b,_op); - reg := R_NO; + reg := R_NONE; end; @@ -187,7 +187,7 @@ uses begin { default order is att } FOperandOrder:=op_att; - {segprefix:=R_NO;}{This may be only for I386 architecture!} + {segprefix:=R_NONE;}{This may be only for I386 architecture!} opsize:=_size; {$ifndef NOAG386BIN} insentry:=nil; @@ -586,10 +586,10 @@ begin ot:=OT_MEMORY or opsize_2_type[i,opsize] else ot:=OT_MEMORY or (ot and OT_SIZE_MASK); - if (ref^.base=R_NO) and (ref^.index=R_NO) then + if (ref^.base=R_NONE) and (ref^.index=R_NONE) then ot:=ot or OT_MEM_OFFS; { fix scalefactor } - if (ref^.index=R_NO) then + if (ref^.index=R_NONE) then ref^.scalefactor:=0 else if (ref^.scalefactor=0) then @@ -821,7 +821,7 @@ begin if m=100 then begin InsSize:=calcsize(insentry); - {if (segprefix<>R_NO) then + {if (segprefix<>R_NONE) then inc(InsSize);}{No segprefix!} { For opsize if size if forced } if (insentry^.flags and (IF_SB or IF_SW or IF_SD))<>0 then @@ -905,8 +905,8 @@ begin begin i:=oper[opidx].ref^.index; b:=oper[opidx].ref^.base; - if not(i in [R_NO,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) or - not(b in [R_NO,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) then + if not(i in [R_NONE,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) or + not(b in [R_NONE,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) then begin NeedAddrPrefix:=true; exit; @@ -947,14 +947,14 @@ end; function process_ea(const input:toper;var output:ea;rfield:longint):boolean; {const regs : array[0..63] of tregister=( - R_MM0, R_EAX, R_AX, R_AL, R_XMM0, R_NO, R_NO, R_NO, - R_MM1, R_ECX, R_CX, R_CL, R_XMM1, R_NO, R_NO, R_NO, - R_MM2, R_EDX, R_DX, R_DL, R_XMM2, R_NO, R_NO, R_NO, - R_MM3, R_EBX, R_BX, R_BL, R_XMM3, R_NO, R_NO, R_NO, - R_MM4, R_ESP, R_SP, R_AH, R_XMM4, R_NO, R_NO, R_NO, - R_MM5, R_EBP, R_BP, R_CH, R_XMM5, R_NO, R_NO, R_NO, - R_MM6, R_ESI, R_SI, R_DH, R_XMM6, R_NO, R_NO, R_NO, - R_MM7, R_EDI, R_DI, R_BH, R_XMM7, R_NO, R_NO, R_NO + R_MM0, R_EAX, R_AX, R_AL, R_XMM0, R_NONE, R_NONE, R_NONE, + R_MM1, R_ECX, R_CX, R_CL, R_XMM1, R_NONE, R_NONE, R_NONE, + R_MM2, R_EDX, R_DX, R_DL, R_XMM2, R_NONE, R_NONE, R_NONE, + R_MM3, R_EBX, R_BX, R_BL, R_XMM3, R_NONE, R_NONE, R_NONE, + R_MM4, R_ESP, R_SP, R_AH, R_XMM4, R_NONE, R_NONE, R_NONE, + R_MM5, R_EBP, R_BP, R_CH, R_XMM5, R_NONE, R_NONE, R_NONE, + R_MM6, R_ESI, R_SI, R_DH, R_XMM6, R_NONE, R_NONE, R_NONE, + R_MM7, R_EDI, R_DI, R_BH, R_XMM7, R_NONE, R_NONE, R_NONE );} var j : longint; @@ -992,7 +992,7 @@ begin o:=input.ref^.offset+input.ref^.offsetfixup; sym:=input.ref^.symbol; { it's direct address } - if (b=R_NO) and (i=R_NO) then + if (b=R_NONE) and (i=R_NONE) then begin { it's a pure offset } output.sib_present:=false; @@ -1003,18 +1003,18 @@ begin { it's an indirection } begin { 16 bit address? } -{ if not((i in [R_NO,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) and - (b in [R_NO,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI])) then +{ if not((i in [R_NONE,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI]) and + (b in [R_NONE,R_EAX,R_EBX,R_ECX,R_EDX,R_EBP,R_ESP,R_ESI,R_EDI])) then Message(asmw_e_16bit_not_supported);} {$ifdef OPTEA} { make single reg base } - if (b=R_NO) and (s=1) then + if (b=R_NONE) and (s=1) then begin b:=i; - i:=R_NO; + i:=R_NONE; end; { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX } -{ if (b=R_NO) and +{ if (b=R_NONE) and (((s=2) and (i<>R_ESP)) or (s=3) or (s=5) or (s=9)) then begin @@ -1029,7 +1029,7 @@ begin end;} {$endif} { wrong, for various reasons } -{ if (i=R_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (i<>R_NO)) then +{ if (i=R_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (i<>R_NONE)) then exit;} { base } { case b of @@ -1038,7 +1038,7 @@ begin R_EDX : base:=2; R_EBX : base:=3; R_ESP : base:=4; - R_NO, + R_NONE, R_EBP : base:=5; R_ESI : base:=6; R_EDI : base:=7; @@ -1051,7 +1051,7 @@ begin R_ECX : index:=1; R_EDX : index:=2; R_EBX : index:=3; - R_NO : index:=4; + R_NONE : index:=4; R_EBP : index:=5; R_ESI : index:=6; R_EDI : index:=7; @@ -1067,7 +1067,7 @@ begin else exit; end; - if (b=R_NO) or + if (b=R_NONE) or ((b<>R_EBP) and (o=0) and (sym=nil)) then md:=0 else @@ -1075,12 +1075,12 @@ begin md:=1 else md:=2; - if (b=R_NO) or (md=2) then + if (b=R_NONE) or (md=2) then output.bytes:=4 else output.bytes:=md;} { SIB needed ? } -{ if (i=R_NO) and (b<>R_ESP) then +{ if (i=R_NONE) and (b<>R_ESP) then begin output.sib_present:=false; output.modrm:=(md shl 6) or (rfield shl 3) or base; diff --git a/compiler/sparc/cgcpu.pas b/compiler/sparc/cgcpu.pas index dbba06a6b0..1fd52b8811 100644 --- a/compiler/sparc/cgcpu.pas +++ b/compiler/sparc/cgcpu.pas @@ -37,55 +37,57 @@ USES node,symconst; TYPE tcgSPARC=CLASS(tcg) - PROCEDURE a_param_reg(list:TAasmOutput;size:tcgsize;r:tregister;CONST LocPara:TParaLocation);OVERRIDE; + FreeParamRegSet:TRegisterSet; + constructor Create; {This method is used to pass a parameter, which is located in a register, to a -routine. It should push/send the parameter to the routine, as required by the +routine. It should give the parameter to the routine, as required by the specific processor ABI. It is overriden for each CPU target. Size : is the size of the operand in the register r : is the register source of the operand nr : is number of that parameter in the routine parameters list starting from one from left to right} - PROCEDURE a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST LocPara:TParaLocation);OVERRIDE; - PROCEDURE a_param_ref(list:TAasmOutput;size:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation);OVERRIDE; - PROCEDURE a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation);OVERRIDE; - PROCEDURE a_call_name(list:TAasmOutput;CONST s:string);OVERRIDE; - PROCEDURE a_call_ref(list:TAasmOutput;CONST ref:TReference);OVERRIDE; - PROCEDURE a_op_const_reg(list:TAasmOutput;Op:TOpCG;a:AWord;reg:TRegister);OVERRIDE; - PROCEDURE a_op_const_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;a:AWord;CONST ref:TReference);OVERRIDE; - PROCEDURE a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);OVERRIDE; - PROCEDURE a_op_ref_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;CONST ref:TReference;reg:TRegister);OVERRIDE; - PROCEDURE a_op_reg_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;reg:TRegister;CONST ref:TReference);OVERRIDE; - PROCEDURE a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;a:aword;src, dst:tregister);OVERRIDE; - PROCEDURE a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);OVERRIDE; + procedure a_param_reg(list:TAasmOutput;size:tcgsize;r:tregister;const LocPara:TParaLocation);override; + PROCEDURE a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST LocPara:TParaLocation);override; + PROCEDURE a_param_ref(list:TAasmOutput;size:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation);override; + PROCEDURE a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation);override; + PROCEDURE a_call_name(list:TAasmOutput;CONST s:string);override; + PROCEDURE a_call_ref(list:TAasmOutput;CONST ref:TReference);override; + PROCEDURE a_op_const_reg(list:TAasmOutput;Op:TOpCG;a:AWord;reg:TRegister);override; + PROCEDURE a_op_const_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;a:AWord;CONST ref:TReference);override; + PROCEDURE a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);override; + PROCEDURE a_op_ref_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;CONST ref:TReference;reg:TRegister);override; + PROCEDURE a_op_reg_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;reg:TRegister;CONST ref:TReference);override; + PROCEDURE a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;a:aword;src, dst:tregister);override; + PROCEDURE a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);override; { move instructions } - PROCEDURE a_load_const_reg(list:TAasmOutput;size:tcgsize;a:aword;reg:tregister);OVERRIDE; - PROCEDURE a_load_const_ref(list:TAasmOutput;size:tcgsize;a:aword;CONST ref:TReference);OVERRIDE; - PROCEDURE a_load_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);OVERRIDE; - PROCEDURE a_load_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);OVERRIDE; - PROCEDURE a_load_reg_reg(list:TAasmOutput;fromsize,size:tcgsize;reg1,reg2:tregister);OVERRIDE; - PROCEDURE a_loadaddr_ref_reg(list:TAasmOutput;CONST ref:TReference;r:tregister);OVERRIDE; + PROCEDURE a_load_const_reg(list:TAasmOutput;size:tcgsize;a:aword;reg:tregister);override; + PROCEDURE a_load_const_ref(list:TAasmOutput;size:tcgsize;a:aword;CONST ref:TReference);override; + PROCEDURE a_load_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);override; + PROCEDURE a_load_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);override; + PROCEDURE a_load_reg_reg(list:TAasmOutput;fromsize,size:tcgsize;reg1,reg2:tregister);override; + PROCEDURE a_loadaddr_ref_reg(list:TAasmOutput;CONST ref:TReference;r:tregister);override; { fpu move instructions } - PROCEDURE a_loadfpu_reg_reg(list:TAasmOutput;reg1, reg2:tregister);OVERRIDE; - PROCEDURE a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);OVERRIDE; - PROCEDURE a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);OVERRIDE; + PROCEDURE a_loadfpu_reg_reg(list:TAasmOutput;reg1, reg2:tregister);override; + PROCEDURE a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);override; + PROCEDURE a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);override; { vector register move instructions } - PROCEDURE a_loadmm_reg_reg(list:TAasmOutput;reg1, reg2:tregister);OVERRIDE; - PROCEDURE a_loadmm_ref_reg(list:TAasmOutput;CONST ref:TReference;reg:tregister);OVERRIDE; - PROCEDURE a_loadmm_reg_ref(list:TAasmOutput;reg:tregister;CONST ref:TReference);OVERRIDE; - PROCEDURE a_parammm_reg(list:TAasmOutput;reg:tregister);OVERRIDE; + PROCEDURE a_loadmm_reg_reg(list:TAasmOutput;reg1, reg2:tregister);override; + PROCEDURE a_loadmm_ref_reg(list:TAasmOutput;CONST ref:TReference;reg:tregister);override; + PROCEDURE a_loadmm_reg_ref(list:TAasmOutput;reg:tregister;CONST ref:TReference);override; + PROCEDURE a_parammm_reg(list:TAasmOutput;reg:tregister);override; { comparison operations } - PROCEDURE a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;reg:tregister;l:tasmlabel);OVERRIDE; - PROCEDURE a_cmp_const_ref_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;CONST ref:TReference;l:tasmlabel);OVERRIDE; - PROCEDURE a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);OVERRIDE; - PROCEDURE a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);OVERRIDE; - PROCEDURE a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);{ OVERRIDE;} - PROCEDURE a_jmp_flags(list:TAasmOutput;CONST f:TResFlags;l:tasmlabel);OVERRIDE; - PROCEDURE g_flags2reg(list:TAasmOutput;Size:TCgSize;CONST f:tresflags;reg:TRegister);OVERRIDE; + PROCEDURE a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;reg:tregister;l:tasmlabel);override; + PROCEDURE a_cmp_const_ref_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;CONST ref:TReference;l:tasmlabel);override; + PROCEDURE a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);override; + PROCEDURE a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);override; + PROCEDURE a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);{ override;} + PROCEDURE a_jmp_flags(list:TAasmOutput;CONST f:TResFlags;l:tasmlabel);override; + PROCEDURE g_flags2reg(list:TAasmOutput;Size:TCgSize;CONST f:tresflags;reg:TRegister);override; procedure g_stackframe_entry(list:TAasmOutput;localsize:LongInt);override; procedure g_restore_frame_pointer(list:TAasmOutput);override; procedure g_return_from_proc(list:TAasmOutput;parasize:aword);override; - PROCEDURE g_concatcopy(list:TAasmOutput;CONST source,dest:TReference;len:aword;delsource,loadref:boolean);OVERRIDE; - class function reg_cgsize(CONST reg:tregister):tcgsize;OVERRIDE; + PROCEDURE g_concatcopy(list:TAasmOutput;CONST source,dest:TReference;len:aword;delsource,loadref:boolean);override; + class function reg_cgsize(CONST reg:tregister):tcgsize;override; PRIVATE PROCEDURE sizes2load(s1:tcgsize;s2:topsize;var op:tasmop;var s3:topsize); PROCEDURE floatload(list:TAasmOutput;t:tcgsize;CONST ref:TReference); @@ -94,10 +96,10 @@ specific processor ABI. It is overriden for each CPU target. PROCEDURE floatstoreops(t:tcgsize;var op:tasmop;var s:topsize); END; TCg64fSPARC=class(tcg64f32) - PROCEDURE a_op64_ref_reg(list:TAasmOutput;op:TOpCG;CONST ref:TReference;reg:TRegister64);OVERRIDE; - PROCEDURE a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);OVERRIDE; - PROCEDURE a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:qWord;regdst:TRegister64);OVERRIDE; - PROCEDURE a_op64_const_ref(list:TAasmOutput;op:TOpCG;value:qWord;CONST ref:TReference);OVERRIDE; + PROCEDURE a_op64_ref_reg(list:TAasmOutput;op:TOpCG;CONST ref:TReference;reg:TRegister64);override; + PROCEDURE a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);override; + PROCEDURE a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:qWord;regdst:TRegister64);override; + PROCEDURE a_op64_const_ref(list:TAasmOutput;op:TOpCG;value:qWord;CONST ref:TReference);override; PROCEDURE get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp); END; CONST @@ -109,6 +111,22 @@ USES globtype,globals,verbose,systems,cutils, symdef,symsym,defbase,paramgr, rgobj,tgobj,rgcpu; +function GetFreeParamReg(var FreeParamRegSet:TRegisterSet):TRegister; + begin + if FreeParamRegSet=[] + then + exit(R_NONE); + GetFreeParamReg:=R_O0; + repeat + GetFreeParamReg:=Succ(GetFreeParamReg); + until GetFreeParamReg in FreeParamRegSet; + Exclude(FreeParamRegSet,GetFreeParamReg); + end; +constructor tcgSPARC.Create; + begin + inherited Create; + FreeParamRegSet:=[R_O0..R_O5]; + end; { we implement the following routines because otherwise we can't } { instantiate the class since it's abstract } PROCEDURE tcgSPARC.a_param_reg(list:TAasmOutput;size:tcgsize;r:tregister;CONST LocPara:TParaLocation); @@ -125,15 +143,19 @@ PROCEDURE tcgSPARC.a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST Loc InternalError(2002032213); List.Concat(taicpu.op_const(A_LD,S_L,a)); END; -PROCEDURE tcgSPARC.a_param_ref(list:TAasmOutput;size:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation); - VAR - tmpreg:TRegister; - BEGIN - IF((Size=OS_32)AND(Size=OS_S32)) - THEN - InternalError(2002032214); - list.concat(taicpu.op_ref(A_LD,S_L,r)); - END; +procedure tcgSPARC.a_param_ref(list:TAasmOutput;size:tcgsize;const r:TReference;const LocPara:TParaLocation); + var + tmpreg:TRegister; + begin + if((Size=OS_32)and(Size=OS_S32)) + then + InternalError(2002032214); + tmpReg:=GetFreeParamReg(FreeParamRegSet); + if tmpReg=R_NONE + then + InternalError(200210030020); + list.concat(taicpu.op_ref_reg(A_LD,S_L,r,tmpReg)); + end; PROCEDURE tcgSPARC.a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation); VAR tmpreg:TRegister; @@ -1082,7 +1104,10 @@ BEGIN END. { $Log$ - Revision 1.8 2002-10-01 21:35:58 mazen + Revision 1.9 2002-10-02 22:20:28 mazen + + out registers allocator for the first 6 scalar parameters which must be passed into %o0..%o5 + + Revision 1.8 2002/10/01 21:35:58 mazen + procedures exiting prologue added and stack frame now restored in the delay slot of the return (JMPL) instruction Revision 1.7 2002/10/01 21:06:29 mazen diff --git a/compiler/sparc/cpubase.pas b/compiler/sparc/cpubase.pas index cd6e44ff36..1ffc1628c1 100644 --- a/compiler/sparc/cpubase.pas +++ b/compiler/sparc/cpubase.pas @@ -242,6 +242,7 @@ TYPE TRegisterSet=SET OF TRegister; reg2strtable=ARRAY[tregister] OF STRING[6]; CONST + R_NO=R_NONE; firstreg = low(tregister); lastreg = high(tregister); std_reg2str:reg2strtable=({$INCLUDE strregs.inc}); @@ -580,7 +581,10 @@ FUNCTION flags_to_cond(CONST f:TResFlags):TAsmCond; END. { $Log$ - Revision 1.9 2002-10-01 21:06:29 mazen + Revision 1.10 2002-10-02 22:20:28 mazen + + out registers allocator for the first 6 scalar parameters which must be passed into %o0..%o5 + + Revision 1.9 2002/10/01 21:06:29 mazen attinst.inc --> strinst.inc Revision 1.8 2002/09/30 19:12:14 mazen diff --git a/compiler/sparc/cpugas.pas b/compiler/sparc/cpugas.pas index a5ad286df7..40a32aba08 100644 --- a/compiler/sparc/cpugas.pas +++ b/compiler/sparc/cpugas.pas @@ -128,7 +128,7 @@ VAR { These are probably not correctly handled under GAS } { should be replaced by coding the segment override } { directly! - DJGPP FAQ } - if segment<>R_NO then + if segment<>R_NONE then s:=gas_reg2str[segment]+':' else s:=''; @@ -144,9 +144,9 @@ VAR else s:=s+tostr(offset); end - else if (index=R_NO) and (base=R_NO) and not assigned(symbol) then + else if (index=R_NONE) and (base=R_NONE) and not assigned(symbol) then s:=s+'0'; - if (index<>R_NO) and (base=R_NO) then + if (index<>R_NONE) and (base=R_NONE) then begin s:=s+'(,'+gas_reg2str[index]; if scalefactor<>0 then @@ -155,10 +155,10 @@ VAR s:=s+')'; end else - if (index=R_NO) and (base<>R_NO) then + if (index=R_NONE) and (base<>R_NONE) then s:=s+'('+gas_reg2str[base]+')' else - if (index<>R_NO) and (base<>R_NO) then + if (index<>R_NONE) and (base<>R_NONE) then begin s:=s+'('+gas_reg2str[base]+','+gas_reg2str[index]; if scalefactor<>0 then diff --git a/compiler/sparc/registers.inc b/compiler/sparc/registers.inc index 98c9ec144d..0e5306e1aa 100644 --- a/compiler/sparc/registers.inc +++ b/compiler/sparc/registers.inc @@ -7,7 +7,10 @@ { Licence : GPL } { Bug report : mazen.neifer.01@supaero.org } {*****************************************************************************} -R_NO +{ + $Id$ +} +R_NONE {General purpose global registers} ,R_G0{This register is usually set to zero and used as a scratch register} ,R_G1,R_G2,R_G3,R_G4,R_G5,R_G6,R_G7 @@ -48,3 +51,9 @@ implementation according to the Assembler Refernce Manual.(MN)} ,R_ASR8,R_ASR9,R_ASR10,R_ASR11,R_ASR12,R_ASR13,R_ASR14,R_ASR15 ,R_ASR16,R_ASR17,R_ASR18,R_ASR19,R_ASR20,R_ASR21,R_ASR22,R_ASR23 ,R_ASR24,R_ASR25,R_ASR26,R_ASR27,R_ASR28,R_ASR29,R_ASR30,R_ASR31 +{ + $Log$ + Revision 1.2 2002-10-02 22:20:28 mazen + + out registers allocator for the first 6 scalar parameters which must be passed into %o0..%o5 + +}