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* Risc-V: make use of sext.h instruction if available

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florian 2024-08-15 21:52:33 +02:00
parent c54d1d4b89
commit 159d97e864
2 changed files with 8 additions and 0 deletions
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4
compiler/riscv32/cgcpu.pas
View File

@ -129,6 +129,10 @@ unit cgcpu;
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (tosize=OS_8) and (fromsize<>OS_8) then
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_S16) then
list.Concat(taicpu.op_reg_reg(A_SEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_S16) and (tcgsize2unsigned[fromsize]=OS_32) then
list.Concat(taicpu.op_reg_reg(A_SEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_16) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_16) and (fromsize<>OS_16) then

4
compiler/riscv64/cgcpu.pas
View File

@ -102,6 +102,10 @@ implementation
list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
else if (tosize=OS_S32) and (tcgsize2unsigned[fromsize]=OS_64) then
list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_S16) then
list.Concat(taicpu.op_reg_reg(A_SEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_S16) and (tcgsize2unsigned[fromsize]=OS_64) then
list.Concat(taicpu.op_reg_reg(A_SEXT_H,reg2,reg1))
else if (tosize=OS_S32) and (fromsize=OS_32) then
list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
else if (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_8) then