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+ support OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_ref

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git-svn-id: trunk@35837 -
This commit is contained in:
nickysn 2017-04-18 15:14:28 +00:00
parent d7b8d8dd54
commit 16af6f03fb
1 changed files with 19 additions and 0 deletions
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19
compiler/x86/cgx86.pas
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@ -2054,6 +2054,17 @@ unit cgx86;
procedure tcgx86.a_op_reg_ref(list : TAsmList; Op: TOpCG; size: TCGSize;reg: TRegister; const ref: TReference);
const
{$if defined(cpu64bitalu)}
REGCX=NR_RCX;
REGCX_Size = OS_64;
{$elseif defined(cpu32bitalu)}
REGCX=NR_ECX;
REGCX_Size = OS_32;
{$elseif defined(cpu16bitalu)}
REGCX=NR_CX;
REGCX_Size = OS_16;
{$endif}
var
tmpref : treference;
begin
@ -2070,6 +2081,14 @@ unit cgx86;
internalerror(200109237);
list.concat(taicpu.op_ref(TOpCG2AsmOp[op],tcgsize2opsize[size],tmpref));
end;
OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
begin
{ Use ecx to load the value, that allows better coalescing }
getcpuregister(list,REGCX);
a_load_reg_reg(list,size,REGCX_Size,reg,REGCX);
list.concat(taicpu.op_reg_ref(TOpCG2AsmOp[op],tcgsize2opsize[size],NR_CL,tmpref));
ungetcpuregister(list,REGCX);
end;
OP_IMUL:
begin
{ this one needs a load/imul/store, which is the default }