paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-08-29 10:00:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

m68k: added some handling for the explicit precision FPU instructions in the spilling and optimizer. fixed a_fsabs and a_fdabs names

Browse Source 
git-svn-id: trunk@42943 -
This commit is contained in:
Károly Balogh 2019-09-08 09:21:17 +00:00
parent 5d9771d141
commit 16fc8c8d9a
3 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
compiler/m68k/aasmcpu.pas
View File

@ -504,13 +504,16 @@ type
result:=operand_write;
A_NEG, A_NEGX, A_EXT, A_EXTB, A_NOT, A_SWAP:
result:=operand_readwrite;
A_TST,A_CMP,A_CMPI,A_BTST:
A_TST, A_CMP, A_CMPI, A_BTST:
begin end; { Do nothing, default operand_read is fine here. }
// FPU opcodes
A_FSXX, A_FSEQ, A_FSNE, A_FSLT, A_FSLE, A_FSGT, A_FSGE:
result:=operand_write;
A_FABS,A_FSQRT,A_FNEG,A_FSIN,A_FCOS:
A_FABS, A_FSABS, A_FDABS,
A_FSQRT, A_FSSQRT, A_FDSQRT,
A_FNEG, A_FSNEG, A_FDNEG,
A_FSIN, A_FCOS:
if ops = 1 then
begin
if opnr = 0 then
@ -519,10 +522,13 @@ type
else
if opnr = 1 then
result:=operand_write;
A_FMOVE:
A_FMOVE, A_FSMOVE, A_FDMOVE:
if opnr=1 then
result:=operand_write;
A_FADD, A_FSUB, A_FMUL, A_FDIV:
A_FADD, A_FSADD, A_FDADD,
A_FSUB, A_FSSUB, A_FDSUB,
A_FMUL, A_FSMUL, A_FDMUL, A_FSGLMUL,
A_FDIV, A_FSDIV, A_FDDIV, A_FSGLDIV:
if opnr=1 then
result:=operand_readwrite;
A_FCMP, A_FTST:

5
compiler/m68k/aoptcpu.pas
View File

@ -411,7 +411,10 @@ unit aoptcpu;
else
result:=result or MaybeRealConstOperSimplify(p);
end;
A_FMOVE,A_FMUL,A_FADD,A_FSUB,A_FDIV:
A_FMOVE,A_FSMOVE,A_FDMOVE,
A_FADD,A_FSADD,A_FDADD,A_FSUB,A_FSSUB,A_FDSUB,
A_FMUL,A_FSMUL,A_FDMUL,A_FDIV,A_FSDIV,A_FDDIV,
A_FSGLMUL,A_FSGLDIV:
begin
if (taicpu(p).opcode = A_FMOVE) and TryToOptimizeMove(p) then
begin

2
compiler/m68k/cpubase.pas
View File

@ -70,7 +70,7 @@ unit cpubase;
a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,a_remu,a_rems,
{ fpu processor instructions - directly supported }
{ ieee aware and misc. condition codes not supported }
a_fabs,fsabs,fdabs,a_fadd,a_fsadd,a_fdadd,
a_fabs,a_fsabs,a_fdabs,a_fadd,a_fsadd,a_fdadd,
a_fbeq,a_fbne,a_fbngt,a_fbgt,a_fbge,a_fbnge,
a_fblt,a_fbnlt,a_fble,a_fbgl,a_fbngl,a_fbgle,a_fbngle,
a_fdbeq,a_fdbne,a_fdbgt,a_fdbngt,a_fdbge,a_fdbnge,