mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-06-01 10:22:32 +02:00
* some fixes to operations with constants
This commit is contained in:
Jonas Maebe
parent
2936e5d81b
commit
17209e05b7
@ -66,8 +66,6 @@ unit cgcpu;
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procedure g_stackframe_entry(list : taasmoutput;localsize : longint);virtual;
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procedure g_restore_frame_pointer(list : taasmoutput);virtual;
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procedure g_return_from_proc(list : taasmoutput;parasize : aword); virtual;
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procedure g_return_from_proc_sysv(list : taasmoutput;parasize : aword);
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procedure g_return_from_proc_mac(list : taasmoutput;parasize : aword);
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procedure a_loadaddress_ref_reg(list : taasmoutput;const ref2 : treference;r : tregister);virtual;
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@ -76,20 +74,22 @@ unit cgcpu;
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private
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{ tries to one immediate instruction to pperform the operation, }
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{ returns false otherwise (then you have to laod the constant }
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procedure g_return_from_proc_sysv(list : taasmoutput;parasize : aword);
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procedure g_return_from_proc_mac(list : taasmoutput;parasize : aword);
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procedure a_op_reg_reg_const32(list: taasmoutput; op: TOpCg;
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dst, src: tregister; a: aword);
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procedure a_op_reg_reg_reg(list: taasmoutput; op: TOpCg; dst, src1,
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src2: tregister);
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{ Make sure ref is a valid reference for the PowerPC and sets the }
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{ base to the value of the index if (base = R_NO). }
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procedure fixref(var ref: treference);
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{ contains the common code of a_load_reg_ref and a_load_ref_reg }
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procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
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var ref: treference);
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ref: treference);
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{ creates the correct branch instruction for a given combination }
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{ of asmcondflags and destination addressing mode }
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@ -338,8 +338,8 @@ const
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begin
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signed := cmp_op in [OC_GT,OC_LT,OC_GTE,OC_LTE];
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If signed Then
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If (longint(a) >= low(smallint)) and (longint(a) <= high(smallint)) Then
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if signed then
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if (longint(a) >= low(smallint)) and (longint(a) <= high(smallint)) Then
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list.concat(taicpu.op_reg_reg_const(A_CMPI,R_CR0,reg,a))
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else
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begin
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@ -417,10 +417,10 @@ const
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internalerror(200109064);
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end;
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end;
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{ load thge conditional register in the destination reg }
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{ load the conditional register in the destination reg }
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list.concat(taicpu.create(op_reg_reg(A_MFCR,reg)));
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{ we will move the bit that has to be tested to bit 0 -> rotate }
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{ left by bitpos+1 (remember, this is big-endian!) }
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{ we will move the bit that has to be tested to bit 31 -> rotate }
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{ left by bitpos+1 (remember, this is big-endian!) }
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if bitpos <> 31 then
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inc(bitpos)
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else
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@ -579,47 +579,6 @@ const
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end;
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end;
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procedure tcgppc.g_return_from_proc_sysv(list : taasmoutput;parasize : aword);
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var regcounter: TRegister;
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begin
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{ release parameter registers }
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for regcounter := R_3 to R_10 do
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a_reg_dealloc(list,regcounter);
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{ AltiVec context restore, not yet implemented !!! }
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{ address of gpr save area to r11 }
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list.concat(taicpu.op_reg_reg_const(A_ADDI,R_11,R_31,-144));
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{ restore gprs }
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list.concat(taicpu.op_sym_ofs(A_BL,newasmsymbol('_restgpr_14'),0));
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{ address of fpr save area to r11 }
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list.concat(taicpu.op_reg_reg_const(A_ADDI,R_11,R_11,144));
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{ restore fprs and return }
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list.concat(taicpu.op_sym_ofs(A_BL,newasmsymbol('_restfpr_14_x'),0));
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end;
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procedure tcgppc.g_return_from_proc_mac(list : taasmoutput;parasize : aword);
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var regcounter: TRegister;
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begin
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{ release parameter registers }
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for regcounter := R_3 to R_10 do
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a_reg_dealloc(list,regcounter);
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{ AltiVec context restore, not yet implemented !!! }
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{ restore SP }
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list.concat(taicpu.op_reg_reg_const(A_ORI,STACK_POINTER,R_31,0));
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{ restore gprs }
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list.concat(taicpu.op_reg_ref(A_LMW,R_13,new_reference(STACK_POINTER,-220)));
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{ restore return address ... }
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list.concat(taicpu.op_reg_ref(A_LWZ,R_0,new_reference(STACK_POINTER,8)));
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{ ... and return from _restf14 }
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list.concat(taicpu.op_sym_ofs(A_B,newasmsymbol('_restf14'),0));
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end;
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procedure tcgppc.a_loadaddress_ref_reg(list : taasmoutput;const ref2 : treference;r : tregister);
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var tmpreg: tregister;
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@ -716,8 +675,7 @@ const
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list.concat(taicpu.op_reg_ref(A_LWZU,tempreg,
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newreference(src)));
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list.concat(taicpu.op_reg_reg_const(A_CMPI,R_CR0,countreg,0));
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list.concat(taicpu.op_reg_ref(A_STWU,tempreg,
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newreference(dst)));
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list.concat(taicpu.op_reg_ref(A_STWU,tempreg,newreference(dst)));
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list.concat(taicpu.op_reg_reg_const(A_SUBI,countreg,countreg,1));
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a_jmp(list,A_BC,CF_NE,lab);
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free_scratch_reg(list,countreg);
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@ -754,6 +712,50 @@ const
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{***************** This is private property, keep out! :) *****************}
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procedure tcgppc.g_return_from_proc_sysv(list : taasmoutput;parasize : aword);
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var
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regcounter: TRegister;
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begin
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{ release parameter registers }
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for regcounter := R_3 to R_10 do
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a_reg_dealloc(list,regcounter);
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{ AltiVec context restore, not yet implemented !!! }
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{ address of gpr save area to r11 }
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list.concat(taicpu.op_reg_reg_const(A_ADDI,R_11,R_31,-144));
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{ restore gprs }
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list.concat(taicpu.op_sym_ofs(A_BL,newasmsymbol('_restgpr_14'),0));
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{ address of fpr save area to r11 }
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list.concat(taicpu.op_reg_reg_const(A_ADDI,R_11,R_11,144));
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{ restore fprs and return }
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list.concat(taicpu.op_sym_ofs(A_BL,newasmsymbol('_restfpr_14_x'),0));
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end;
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procedure tcgppc.g_return_from_proc_mac(list : taasmoutput;parasize : aword);
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var
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regcounter: TRegister;
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begin
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{ release parameter registers }
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for regcounter := R_3 to R_10 do
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a_reg_dealloc(list,regcounter);
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{ AltiVec context restore, not yet implemented !!! }
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{ restore SP }
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list.concat(taicpu.op_reg_reg_const(A_ORI,STACK_POINTER,R_31,0));
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{ restore gprs }
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list.concat(taicpu.op_reg_ref(A_LMW,R_13,new_reference(STACK_POINTER,-220)));
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{ restore return address ... }
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list.concat(taicpu.op_reg_ref(A_LWZ,R_0,new_reference(STACK_POINTER,8)));
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{ ... and return from _restf14 }
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list.concat(taicpu.op_sym_ofs(A_B,newasmsymbol('_restf14'),0));
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end;
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procedure tcgppc.fixref(var ref: treference);
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begin
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@ -778,31 +780,33 @@ const
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{ find out whether a is of the form 11..00..11b or 00..11...00. If }
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{ that's the case, we can use rlwinm to do an AND operation }
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function get_rlwinm_const: boolean;
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function get_rlwi_const: boolean;
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var
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temp, testbit, compare: longint;
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temp, testbit: longint;
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compare: boolean;
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begin
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get_rlwinm_const := false;
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get_rlwi_const := false;
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{ start with the lowest bit }
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testbit := 1;
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{ check its value }
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compare := a and testbit;
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{ find out how long the run of bits with this value is }
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compare := boolean(a and testbit);
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{ find out how long the run of bits with this value is }
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{ (it's impossible that all bits are 1 or 0, because in that case }
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{ this function wouldn't have been called) }
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l1 := 31;
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while (a and testbit) = compare do
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while (((a and testbit) <> 0) = compare) do
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begin
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testbit := testbit shl 1;
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dec(l1);
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end;
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{ check the length of the run of bits that come next }
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compare := compare xor 1;
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testbit := testbit shl 1;
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l2 := l1 - 1;
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while (a and testbit) = compare) and
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(l2 > 0) do
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{ check the length of the run of bits that comes next }
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compare := not compare;
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l2 := l1;
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while (((a and testbit) <> 0) = compare) and
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(l2 >= 0) do
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begin
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testbit := testbit shl 1;
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dec(l2);
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@ -810,30 +814,32 @@ const
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{ and finally the check whether the rest of the bits all have the }
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{ same value }
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compare := compare xor 1;
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temp := l2 - 1;
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if temp > 0 then
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if (a shr (31-temp)) <> ((-compare) shr (31-temp)) then
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compare := not compare;
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temp := l2;
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if temp >= 0 then
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if (a shr (31-temp)) <> ((-ord(compare)) shr (31-temp)) then
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exit;
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{ we have done "compare xor 1 xor 1", so compare is back to its }
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{ we have done "not(not(compare))", so compare is back to its }
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{ initial value. If the lowest bit was 0, a is of the form }
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{ 00..11..00 and we need "rlwinm reg,reg,0,l2,l1-1", (-1 }
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{ because l1 then contains the position of the first zero of }
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{ the second run instead of that of the last 1) so switch l1 }
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{ and l2 in that case (we will generate }
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{ "rlwinm reg,reg,0,l1,l2") }
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if compare = 0 then
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{ 00..11..00 and we need "rlwinm reg,reg,0,l2+1,l1", (+1 }
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{ because l2 now contains the position of the last zero of the }
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{ first run instead of that of the first 1) so switch l1 and l2 }
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{ in that case (we will generate "rlwinm reg,reg,0,l1,l2") }
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if not compare then
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begin
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temp := l1-1;
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l1 := l2;
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temp := l1;
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l1 := l2+1;
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l2 := temp;
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end
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else
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{ a is of the form 11..00.11 -> l2 contains the position of }
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{ the first zero instead of of the last 1 of the first run }
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dec(l2);
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get_rlwinm_const := true;
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{ otherwise, l1 currently contains the position of the last }
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{ zero instead of that of the first 1 of the second run -> +1 }
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inc(l1);
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{ the following is the same as "if l1 = -1 then l1 := 31;" }
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l1 := l1 and 31;
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l2 := l2 and 31;
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get_rlwi_const := true;
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end;
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var
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@ -842,40 +848,56 @@ const
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useReg: boolean;
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begin
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useReg := true;
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useReg := false;
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ophi := TOpCG2AsmOpConstHi[op];
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oplo := TOpCG2AsmOpConstLo[op];
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{ constants in a PPC instruction are always interpreted as signed }
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{ 16bit values, so if the value is between low(smallint) and }
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{ high(smallint), it's easy }
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if (longint(a) >= low(smallint)) and
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(longint(a) <= high(smallint)) then
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begin
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,a));
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exit;
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end;
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{ all basic constant instructions also have a shifted form that }
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{ works only on the highest 16bits, so if low(a) is 0, we can }
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{ use that one }
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if (low(a) = 0) then
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begin
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list.concat(taicpu.op_reg_reg(ophi,reg1,reg2,high(a)));
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exit;
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end;
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oplo := TOpCG2AsmOpConstLo[op];
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{ otherwise, the instructinos we can generate depend on the }
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{ operation }
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case op of
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OP_ADD,OP_SUB:
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if (longint(a) >= low(smallint)) and (longint(a) <= high(smallint)) then
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,a))
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begin
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,low(a)));
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list.concat(taicpu.op_reg_reg_const(ophi,reg1,reg1,
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high(a) + ord(smallint(a) < 0)));
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end;
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OP_OR:
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{ try to use rlwimi }
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if get_rlwi_const then
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list.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,reg1,
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reg2,0,l1,l2))
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else
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begin
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,low(a)));
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list.concat(taicpu.op_reg_reg_const(ophi,reg1,reg1,
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high(a) + ord(smallint(a) < 0)));
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end;
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OP_OR,OP_XOR:
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if (longint(a) >= 0) and (longint(a) <= high(smallint)) then
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,a))
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else
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useReg := false;
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useReg := true;
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OP_AND:
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if (longint(a) >= low(smallint)) and (longint(a) <= 0) then
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list.concat(taicpu.op_reg_reg_const(oplo,reg1,reg2,a))
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else if get_rlwinm_const then
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list.concat(taicpu.op_reg_reg_const_const_const(
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a_rlwinm,reg1,reg2,0,l1,l2))
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{ try to use rlwinm }
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if get_rlwi_const then
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list.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,reg1,
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reg2,0,l1,l2))
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else
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useReg := false;
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useReg := true;
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OP_XOR:
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useReg := true;
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else
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internalerror(200109091);
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end;
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{ if all else failed, load the constant in a register and then }
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{ perform the operation }
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if useReg then
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begin
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scratchreg := get_scratch_reg(list);
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@ -887,7 +909,7 @@ const
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procedure tcgppc.a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
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dest, src1, src2: tregister);
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dst, src1, src2: tregister);
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const
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op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
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@ -904,7 +926,7 @@ const
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procedure tcgppc.a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
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var ref: treference);
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ref: treference);
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var
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tmpreg: tregister;
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@ -947,8 +969,8 @@ const
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end.
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{
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$Log$
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Revision 1.4 2001-09-09 17:10:25 jonas
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* some more things implemented
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Revision 1.5 2001-09-16 10:33:21 jonas
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* some fixes to operations with constants
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Revision 1.3 2001/09/06 15:25:55 jonas
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* changed type of tcg from object to class -> abstract methods are now
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