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https://gitlab.com/freepascal.org/fpc/source.git
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* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.
+ Enable registers %i0..%i5 and %o7 for use by reg.allocator. Some notable properties of this implementation are: o pi_needs_got flag can be safely set during pass 2, so not setting it occasionally in pass 1 does not result in internal error. o Reg.allocator configuration is independent from PIC. If procedure requires GOT, register %l7 is allocated at the prologue, making it unavailable to RA. o GOT is stored in fixed %l7 register, but it is trivial to switch over to virtual register. git-svn-id: trunk@26293 -
This commit is contained in:
sergei
parent
1a3b46967e
commit
176d8434e4
@ -43,7 +43,6 @@ interface
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function getfpuregister(list:TAsmList;size:Tcgsize):Tregister;override;
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{ sparc special, needed by cg64 }
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procedure make_simple_ref(list:TAsmList;var ref: treference);
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procedure make_simple_ref_sparc(list:TAsmList;var ref: treference;loadaddr : boolean;addrreg : tregister);
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procedure handle_load_store(list:TAsmList;isstore:boolean;op: tasmop;reg:tregister;ref: treference);
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procedure handle_reg_const_reg(list:TAsmList;op:Tasmop;src:tregister;a:tcgint;dst:tregister);
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{ parameter }
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@ -142,8 +141,6 @@ implementation
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function TCgSparc.IsSimpleRef(const ref:treference):boolean;
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begin
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if (ref.base=NR_NO) and (ref.index<>NR_NO) then
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InternalError(2002100804);
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result :=not(assigned(ref.symbol))and
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(((ref.index = NR_NO) and
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(ref.offset >= simm13lo) and
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@ -154,181 +151,113 @@ implementation
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procedure tcgsparc.make_simple_ref(list:TAsmList;var ref: treference);
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begin
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make_simple_ref_sparc(list,ref,false,NR_NO);
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end;
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procedure tcgsparc.make_simple_ref_sparc(list:TAsmList;var ref: treference;loadaddr : boolean;addrreg : tregister);
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var
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tmpreg,tmpreg2 : tregister;
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tmpref : treference;
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need_add_got,need_got_load : boolean;
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href: treference;
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hreg,hreg2: tregister;
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begin
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if loadaddr then
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tmpreg:=addrreg
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else
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tmpreg:=NR_NO;
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need_add_got:=false;
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need_got_load:=false;
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{ Be sure to have a base register }
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if (ref.refaddr<>addr_no) then
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InternalError(2013022802);
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if (ref.base=NR_NO) then
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begin
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ref.base:=ref.index;
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ref.index:=NR_NO;
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end;
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if (cs_create_pic in current_settings.moduleswitches) and
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(tf_pic_uses_got in target_info.flags) and
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use_unlimited_pic_mode and
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assigned(ref.symbol) then
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if IsSimpleRef(ref) then
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exit;
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if (ref.symbol=nil) then
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begin
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if not(pi_needs_got in current_procinfo.flags) then
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begin
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{$ifdef CHECK_PIC}
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internalerror(200501161);
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{$endif CHECK_PIC}
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include(current_procinfo.flags,pi_needs_got);
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end;
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if current_procinfo.got=NR_NO then
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current_procinfo.got:=NR_L7;
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need_got_load:=true;
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need_add_got:=true;
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end;
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if (cs_create_pic in current_settings.moduleswitches) and
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(tf_pic_uses_got in target_info.flags) and
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not use_unlimited_pic_mode and
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assigned(ref.symbol) then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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reference_reset(tmpref,ref.alignment);
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tmpref.symbol:=ref.symbol;
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tmpref.refaddr:=addr_pic;
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if not(pi_needs_got in current_procinfo.flags) then
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begin
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{$ifdef CHECK_PIC}
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internalerror(200501161);
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{$endif CHECK_PIC}
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include(current_procinfo.flags,pi_needs_got);
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end;
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if current_procinfo.got=NR_NO then
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current_procinfo.got:=NR_L7;
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tmpref.index:=current_procinfo.got;
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list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
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ref.symbol:=nil;
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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hreg:=getintregister(list,OS_INT);
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if (ref.index=NR_NO) then
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a_load_const_reg(list,OS_INT,ref.offset,hreg)
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else
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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ref.base:=tmpreg;
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end;
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end;
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{ When need to use SETHI, do it first }
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if assigned(ref.symbol) or
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(ref.offset<simm13lo) or
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(ref.offset>simm13hi) then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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reference_reset(tmpref,ref.alignment);
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tmpref.symbol:=ref.symbol;
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if not need_got_load then
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tmpref.offset:=ref.offset;
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tmpref.refaddr:=addr_high;
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list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,tmpreg));
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if (ref.offset=0) and (ref.index=NR_NO) and
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(ref.base=NR_NO) and not need_add_got then
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begin
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ref.refaddr:=addr_low;
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end
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else
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begin
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{ Load the low part is left }
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tmpref.refaddr:=addr_low;
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list.concat(taicpu.op_reg_ref_reg(A_OR,tmpreg,tmpref,tmpreg));
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if not need_got_load then
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ref.offset:=0;
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{ symbol is loaded }
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ref.symbol:=nil;
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end;
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if need_add_got then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,current_procinfo.got,tmpreg));
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need_add_got:=false;
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end;
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if need_got_load then
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begin
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tmpref.refaddr:=addr_no;
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tmpref.base:=tmpreg;
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tmpref.symbol:=nil;
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list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
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need_got_load:=false;
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if (ref.offset<simm13lo) or
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(ref.offset>simm13hi) then
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if (ref.offset<simm13lo) or (ref.offset>simm13hi-sizeof(pint)) then
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begin
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tmpref.symbol:=nil;
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tmpref.offset:=ref.offset;
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tmpref.base:=tmpreg;
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tmpref.refaddr := addr_high;
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tmpreg2:=GetIntRegister(list,OS_INT);
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a_load_const_reg(list,OS_INT,ref.offset,tmpreg2);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,tmpreg2,tmpreg));
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a_load_const_reg(list,OS_INT,ref.offset,hreg);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,hreg));
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end
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else
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list.concat(taicpu.op_reg_const_reg(A_ADD,ref.index,ref.offset,hreg));
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end;
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if (ref.base=NR_NO) then
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ref.base:=hreg
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else
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ref.index:=hreg;
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ref.offset:=0;
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exit;
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end;
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reference_reset_symbol(href,ref.symbol,ref.offset,ref.alignment);
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hreg:=getintregister(list,OS_INT);
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if not (cs_create_pic in current_settings.moduleswitches) then
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begin
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{ absolute loads allow any offset to be encoded into relocation }
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href.refaddr:=addr_high;
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list.concat(taicpu.op_ref_reg(A_SETHI,href,hreg));
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if (ref.base=NR_NO) and (ref.index=NR_NO) then
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begin
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ref.base:=hreg;
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ref.refaddr:=addr_low;
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exit;
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end;
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{ base present -> load the entire address and use it as index }
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href.refaddr:=addr_low;
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list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,href,hreg));
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ref.symbol:=nil;
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ref.offset:=0;
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if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.index,hreg,hreg));
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ref.index:=hreg;
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end
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else
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begin
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include(current_procinfo.flags,pi_needs_got);
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href.offset:=0;
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if use_unlimited_pic_mode then
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begin
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href.refaddr:=addr_high;
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list.concat(taicpu.op_ref_reg(A_SETHI,href,hreg));
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href.refaddr:=addr_low;
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list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,href,hreg));
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reference_reset_base(href,hreg,0,sizeof(pint));
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href.index:=current_procinfo.got;
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end
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else
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begin
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href.base:=current_procinfo.got;
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href.refaddr:=addr_pic;
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end;
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list.concat(taicpu.op_ref_reg(A_LD,href,hreg));
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ref.symbol:=nil;
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{ hreg now holds symbol address. Add remaining members. }
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if (ref.offset>=simm13lo) and (ref.offset<=simm13hi-sizeof(pint)) then
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begin
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if (ref.base=NR_NO) then
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ref.base:=hreg
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else
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begin
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if (ref.offset<>0) then
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list.concat(taicpu.op_reg_const_reg(A_ADD,hreg,ref.offset,hreg));
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if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,hreg));
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ref.index:=hreg;
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ref.offset:=0;
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end;
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end;
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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else
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else { large offset, need another register to deal with it }
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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ref.base:=tmpreg;
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end;
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end;
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if need_add_got then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,current_procinfo.got,tmpreg));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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end;
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if need_got_load then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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list.concat(taicpu.op_ref_reg(A_LD,ref,tmpreg));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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end;
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if (ref.base<>NR_NO) or loadaddr then
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begin
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if loadaddr then
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begin
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if ref.index<>NR_NO then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,tmpreg));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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if ref.offset<>0 then
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list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,tmpreg));
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end
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else if (ref.index<>NR_NO) and
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((ref.offset<>0) or assigned(ref.symbol)) then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,tmpreg));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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hreg2:=getintregister(list,OS_INT);
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a_load_const_reg(list,OS_INT,ref.offset,hreg2);
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if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg2,ref.index,hreg2));
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if (ref.base<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg2,ref.base,hreg2));
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ref.base:=hreg;
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ref.index:=hreg2;
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ref.offset:=0;
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end;
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end;
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end;
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@ -376,21 +305,11 @@ implementation
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begin
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inherited init_register_allocators;
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if (cs_create_pic in current_settings.moduleswitches) and
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assigned(current_procinfo) and
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(pi_needs_got in current_procinfo.flags) then
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begin
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current_procinfo.got:=NR_L7;
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6],
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first_int_imreg,[]);
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end
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else
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7],
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first_int_imreg,[]);
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,RS_O7,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7,
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RS_I0,RS_I1,RS_I2,RS_I3,RS_I4,RS_I5],
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first_int_imreg,[]);
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBFS,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
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@ -739,164 +658,89 @@ implementation
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procedure TCgSparc.a_loadaddr_ref_reg(list : TAsmList;const ref : TReference;r : tregister);
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var
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tmpref,href : treference;
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hreg,tmpreg,hreg2 : tregister;
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need_got,need_got_load : boolean;
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href: treference;
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hreg: tregister;
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begin
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href:=ref;
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{$ifdef TEST_SIMPLE_SPARC}
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make_simple_ref_sparc(list,href,true,r);
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{$else}
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need_got:=false;
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need_got_load:=false;
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if (href.base=NR_NO) and (href.index<>NR_NO) then
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if (ref.base=NR_NO) and (ref.index<>NR_NO) then
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internalerror(200306171);
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if (cs_create_pic in current_settings.moduleswitches) and
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(tf_pic_uses_got in target_info.flags) and
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use_unlimited_pic_mode and
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assigned(ref.symbol) then
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if (ref.symbol=nil) then
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begin
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if not(pi_needs_got in current_procinfo.flags) then
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if (ref.base<>NR_NO) then
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begin
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{$ifdef CHECK_PIC}
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internalerror(200501161);
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{$endif CHECK_PIC}
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include(current_procinfo.flags,pi_needs_got);
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end;
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if current_procinfo.got=NR_NO then
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current_procinfo.got:=NR_L7;
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need_got_load:=true;
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need_got:=true;
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if (ref.offset<simm13lo) or (ref.offset>simm13hi) then
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begin
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hreg:=getintregister(list,OS_INT);
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a_load_const_reg(list,OS_INT,ref.offset,hreg);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.base,r));
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if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.index,r));
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end
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else if (ref.offset<>0) then
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begin
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list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,r));
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if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.index,r));
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end
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else if (ref.index<>NR_NO) then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,r))
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else
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a_load_reg_reg(list,OS_INT,OS_INT,ref.base,r); { (try to) emit optimizable move }
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end
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else
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a_load_const_reg(list,OS_INT,ref.offset,r);
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exit;
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end;
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if (cs_create_pic in current_settings.moduleswitches) and
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(tf_pic_uses_got in target_info.flags) and
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not use_unlimited_pic_mode and
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assigned(href.symbol) then
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reference_reset_symbol(href,ref.symbol,ref.offset,ref.alignment);
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if (cs_create_pic in current_settings.moduleswitches) then
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begin
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tmpreg:=GetIntRegister(list,OS_ADDR);
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reference_reset(tmpref,href.alignment);
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tmpref.symbol:=href.symbol;
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tmpref.refaddr:=addr_pic;
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if not(pi_needs_got in current_procinfo.flags) then
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include(current_procinfo.flags,pi_needs_got);
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href.offset:=0;
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if use_unlimited_pic_mode then
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begin
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{$ifdef CHECK_PIC}
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internalerror(200501161);
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{$endif CHECK_PIC}
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include(current_procinfo.flags,pi_needs_got);
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end;
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if current_procinfo.got=NR_NO then
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current_procinfo.got:=NR_L7;
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tmpref.base:=current_procinfo.got;
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list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
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href.symbol:=nil;
|
||||
if (href.index<>NR_NO) then
|
||||
begin
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,href.index,tmpreg));
|
||||
href.index:=tmpreg;
|
||||
href.refaddr:=addr_high;
|
||||
list.concat(taicpu.op_ref_reg(A_SETHI,href,r));
|
||||
href.refaddr:=addr_low;
|
||||
list.concat(taicpu.op_reg_ref_reg(A_OR,r,href,r));
|
||||
reference_reset_base(href,r,0,sizeof(pint));
|
||||
href.index:=current_procinfo.got;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if href.base<>NR_NO then
|
||||
href.index:=tmpreg
|
||||
else
|
||||
href.base:=tmpreg;
|
||||
href.base:=current_procinfo.got;
|
||||
href.refaddr:=addr_pic; { should it be done THAT way?? }
|
||||
end;
|
||||
end;
|
||||
|
||||
{ At least big offset (need SETHI), maybe base and maybe index }
|
||||
if assigned(href.symbol) or
|
||||
(href.offset<simm13lo) or
|
||||
(href.offset>simm13hi) then
|
||||
begin
|
||||
hreg:=GetAddressRegister(list);
|
||||
reference_reset(tmpref,href.alignment);
|
||||
tmpref.symbol := href.symbol;
|
||||
if not need_got_load then
|
||||
tmpref.offset := href.offset;
|
||||
tmpref.refaddr := addr_high;
|
||||
list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,hreg));
|
||||
{ Only the low part is left }
|
||||
tmpref.refaddr:=addr_low;
|
||||
list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,tmpref,hreg));
|
||||
if need_got then
|
||||
{ load contents of GOT slot }
|
||||
list.concat(taicpu.op_ref_reg(A_LD,href,r));
|
||||
{ add original base/index, if any }
|
||||
if (ref.base<>NR_NO) then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.base,r));
|
||||
if (ref.index<>NR_NO) then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.index,r));
|
||||
{ finally, add offset }
|
||||
if (ref.offset<simm13lo) or (ref.offset>simm13hi) then
|
||||
begin
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,current_procinfo.got,hreg));
|
||||
need_got:=false;
|
||||
end;
|
||||
if need_got_load then
|
||||
begin
|
||||
tmpref.symbol:=nil;
|
||||
tmpref.base:=hreg;
|
||||
tmpref.refaddr:=addr_no;
|
||||
list.concat(taicpu.op_ref_reg(A_LD,tmpref,hreg));
|
||||
need_got_load:=false;
|
||||
if (href.offset<simm13lo) or
|
||||
(href.offset>simm13hi) then
|
||||
begin
|
||||
tmpref.symbol:=nil;
|
||||
tmpref.offset:=href.offset;
|
||||
tmpref.refaddr := addr_high;
|
||||
hreg2:=GetIntRegister(list,OS_INT);
|
||||
a_load_const_reg(list,OS_INT,href.offset,hreg2);
|
||||
{ Only the low part is left }
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,hreg2,hreg));
|
||||
end
|
||||
else if (href.offset<>0) then
|
||||
begin
|
||||
list.concat(taicpu.op_reg_const_reg(A_ADD,hreg,href.offset,hreg));
|
||||
end;
|
||||
end;
|
||||
if href.base<>NR_NO then
|
||||
begin
|
||||
if href.index<>NR_NO then
|
||||
begin
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,hreg));
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
|
||||
end
|
||||
else
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,r));
|
||||
hreg:=getintregister(list,OS_INT);
|
||||
a_load_const_reg(list,OS_INT,ref.offset,hreg);
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,r,r));
|
||||
end
|
||||
else
|
||||
begin
|
||||
if hreg<>r then
|
||||
a_load_reg_reg(list,OS_ADDR,OS_ADDR,hreg,r);
|
||||
end;
|
||||
else if (ref.offset<>0) then
|
||||
list.concat(taicpu.op_reg_const_reg(A_ADD,r,ref.offset,r));
|
||||
end
|
||||
else
|
||||
{ At least small offset, maybe base and maybe index }
|
||||
if href.offset<>0 then
|
||||
begin
|
||||
if href.base<>NR_NO then
|
||||
begin
|
||||
if href.index<>NR_NO then
|
||||
begin
|
||||
hreg:=GetAddressRegister(list);
|
||||
list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,hreg));
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
|
||||
end
|
||||
else
|
||||
list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,r));
|
||||
end
|
||||
else
|
||||
list.concat(taicpu.op_const_reg(A_MOV,href.offset,r));
|
||||
end
|
||||
else
|
||||
{ Both base and index }
|
||||
if href.index<>NR_NO then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,href.base,href.index,r))
|
||||
else
|
||||
{ Only base }
|
||||
if href.base<>NR_NO then
|
||||
a_load_reg_reg(list,OS_ADDR,OS_ADDR,href.base,r)
|
||||
else
|
||||
{ only offset, can be generated by absolute }
|
||||
a_load_const_reg(list,OS_ADDR,href.offset,r);
|
||||
if need_got then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,r,current_procinfo.got,r));
|
||||
if need_got_load then
|
||||
list.concat(taicpu.op_reg_reg(A_LD,r,r));
|
||||
{$endif}
|
||||
begin
|
||||
{ load symbol+offset }
|
||||
href.refaddr:=addr_high;
|
||||
list.concat(taicpu.op_ref_reg(A_SETHI,href,r));
|
||||
href.refaddr:=addr_low;
|
||||
list.concat(taicpu.op_reg_ref_reg(A_OR,r,href,r));
|
||||
{ add original base/index, if any }
|
||||
if (ref.base<>NR_NO) then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.base,r));
|
||||
if (ref.index<>NR_NO) then
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref.index,r));
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -1261,9 +1105,9 @@ implementation
|
||||
hl : tasmlabel;
|
||||
begin
|
||||
if (cs_create_pic in current_settings.moduleswitches) and
|
||||
(pi_needs_got in current_procinfo.flags) then
|
||||
((pi_needs_got in current_procinfo.flags) or
|
||||
(current_procinfo.procdef.proctypeoption=potype_unitfinalize)) then
|
||||
begin
|
||||
current_procinfo.got:=NR_L7;
|
||||
current_asmdata.getjumplabel(hl);
|
||||
list.concat(taicpu.op_sym(A_CALL,hl));
|
||||
{ ABI recommends the following sequence:
|
||||
@ -1279,6 +1123,8 @@ implementation
|
||||
ref.offset:=8;
|
||||
list.concat(Taicpu.Op_reg_ref_reg(A_OR,NR_L7,ref,NR_L7));
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_L7,NR_O7,NR_L7));
|
||||
{ allocate NR_L7, so reg.allocator does not see it as available }
|
||||
list.concat(tai_regalloc.alloc(NR_L7,nil));
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -83,91 +83,53 @@ implementation
|
||||
|
||||
|
||||
function TSPARCInstrWriter.GetReferenceString(var ref:TReference):string;
|
||||
var
|
||||
asm_comment : string;
|
||||
begin
|
||||
GetReferenceString:='';
|
||||
asm_comment:='';
|
||||
with ref do
|
||||
result:='';
|
||||
if assigned(ref.symbol) then
|
||||
result:=ref.symbol.name;
|
||||
if (ref.offset<0) then
|
||||
result:=result+tostr(ref.offset)
|
||||
else if (ref.offset>0) then
|
||||
begin
|
||||
if (base=NR_NO) and (index=NR_NO) then
|
||||
if assigned(ref.symbol) then
|
||||
result:=result+'+';
|
||||
result:=result+tostr(ref.offset);
|
||||
end
|
||||
{ asmreader appears to treat literal numbers as references }
|
||||
else if (ref.symbol=nil) and (ref.base=NR_NO) and (ref.index=NR_NO) then
|
||||
result:='0';
|
||||
|
||||
case ref.refaddr of
|
||||
addr_high:
|
||||
result:='%hi('+result+')';
|
||||
addr_low:
|
||||
result:='%lo('+result+')';
|
||||
end;
|
||||
|
||||
if assigned(ref.symbol) or (ref.offset<>0) then
|
||||
begin
|
||||
if (ref.base<>NR_NO) then
|
||||
begin
|
||||
if assigned(symbol) then
|
||||
GetReferenceString:=symbol.name;
|
||||
if offset>0 then
|
||||
GetReferenceString:=GetReferenceString+'+'+ToStr(offset)
|
||||
else if offset<0 then
|
||||
GetReferenceString:=GetReferenceString+ToStr(offset);
|
||||
case refaddr of
|
||||
addr_high:
|
||||
GetReferenceString:='%hi('+GetReferenceString+')';
|
||||
addr_low:
|
||||
GetReferenceString:='%lo('+GetReferenceString+')';
|
||||
addr_pic:
|
||||
begin
|
||||
asm_comment:='addr_pic should use %l7 register as base or index: '+GetReferenceString;
|
||||
Comment(V_Warning,asm_comment);
|
||||
GetReferenceString:='%l7+'+GetReferenceString;
|
||||
end;
|
||||
end;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (base=NR_NO) and (index<>NR_NO) then
|
||||
begin
|
||||
base:=index;
|
||||
index:=NR_NO;
|
||||
end;
|
||||
{$ifdef extdebug}
|
||||
if assigned(symbol) and
|
||||
not(refaddr in [addr_pic,addr_low]) then
|
||||
internalerror(2003052601);
|
||||
{$endif extdebug}
|
||||
GetReferenceString:=GetReferenceString+gas_regname(base);
|
||||
if index=NR_NO then
|
||||
begin
|
||||
{ if (Offset<simm13lo) or (Offset>simm13hi) then
|
||||
internalerror(2003053008); }
|
||||
if offset>0 then
|
||||
GetReferenceString:=GetReferenceString+'+'+ToStr(offset)
|
||||
else if offset<0 then
|
||||
GetReferenceString:=GetReferenceString+ToStr(offset);
|
||||
{
|
||||
else if (offset=0) and not(assigned(symbol)) then
|
||||
GetReferenceString:=GetReferenceString+ToStr(offset);
|
||||
}
|
||||
if assigned(symbol) then
|
||||
begin
|
||||
if refaddr=addr_low then
|
||||
GetReferenceString:='%lo('+symbol.name+')+'+GetReferenceString
|
||||
else if refaddr=addr_pic then
|
||||
begin
|
||||
if assigned(current_procinfo) and (base <> current_procinfo.got) then
|
||||
begin
|
||||
asm_comment:=' pic address should use %l7 register: '+GetReferenceString;
|
||||
Comment(V_Warning,asm_comment);
|
||||
end;
|
||||
GetReferenceString:=GetReferenceString+'+'+symbol.name;
|
||||
end
|
||||
else
|
||||
GetReferenceString:=symbol.name+'+'+GetReferenceString;
|
||||
end;
|
||||
end
|
||||
if (ref.index<>NR_NO) then
|
||||
InternalError(2013013001);
|
||||
if (result[1]='-') then
|
||||
result:=gas_regname(ref.base)+result
|
||||
else
|
||||
begin
|
||||
{$ifdef extdebug}
|
||||
if (Offset<>0) or assigned(symbol) then
|
||||
internalerror(2003052603);
|
||||
{$endif extdebug}
|
||||
GetReferenceString:=GetReferenceString+'+'+gas_regname(index);
|
||||
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
if asm_comment <> '' then
|
||||
result:=gas_regname(ref.base)+'+'+result;
|
||||
end
|
||||
else if (ref.index<>NR_NO) then
|
||||
InternalError(2013122501);
|
||||
end
|
||||
else
|
||||
begin
|
||||
owner.AsmWrite(target_asm.comment+' '+asm_comment);
|
||||
owner.AsmLn;
|
||||
if (ref.base<>NR_NO) then
|
||||
begin
|
||||
result:=gas_regname(ref.base);
|
||||
if (ref.index<>NR_NO) then
|
||||
result:=result+'+'+gas_regname(ref.index);
|
||||
end
|
||||
else if (ref.index<>NR_NO) then
|
||||
result:=gas_regname(ref.index);
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -41,12 +41,14 @@ implementation
|
||||
|
||||
uses
|
||||
systems,globals,
|
||||
cpubase,cgbase,
|
||||
tgobj,paramgr,symconst;
|
||||
|
||||
constructor tsparcprocinfo.create(aparent:tprocinfo);
|
||||
begin
|
||||
inherited create(aparent);
|
||||
maxpushedparasize:=0;
|
||||
got:=NR_L7;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user