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* Change spill_* routines to return Taicpu instead of Tai to increase

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strong typing.
  * Fix PowerPC R0 register allocation

git-svn-id: trunk@7317 -
This commit is contained in:
daniel 2007-05-12 15:43:16 +00:00
parent 821c91c230
commit 182fca72f2
7 changed files with 55 additions and 31 deletions

8
compiler/arm/aasmcpu.pas
View File

@ -228,8 +228,8 @@ uses
{ nothing to add }
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
@ -499,7 +499,7 @@ implementation
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :
@ -515,7 +515,7 @@ implementation
end;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :

8
compiler/m68k/aasmcpu.pas
View File

@ -98,8 +98,8 @@ type
procedure InitAsm;
procedure DoneAsm;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
implementation
@ -532,7 +532,7 @@ type
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :
@ -548,7 +548,7 @@ type
end;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :

8
compiler/ppcgen/aasmcpu.pas
View File

@ -96,8 +96,8 @@ uses
procedure DoneAsm;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
procedure fixup_jmps(list: TAsmList);
@ -436,7 +436,7 @@ uses cutils, cclasses;
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER:
@ -453,7 +453,7 @@ uses cutils, cclasses;
end;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER:

24
compiler/ppcgen/rgcpu.pas
View File

@ -59,6 +59,7 @@ unit rgcpu;
helplist : TAsmList;
l : tasmlabel;
hreg : tregister;
ins : Taicpu;
begin
if (spilltemp.offset<low(smallint)) or
(spilltemp.offset>high(smallint)) then
@ -71,18 +72,23 @@ unit rgcpu;
if getregtype(tempreg)=R_INTREGISTER then
begin
hreg:=getregisterinline(helplist,R_SUBWHOLE);
add_edge(getsupreg(hreg),RS_R0);
{Done by add_cpu_interferences now.
add_edge(getsupreg(hreg),RS_R0);}
end
else
hreg:=cg.getintregister(helplist,OS_ADDR);
reference_reset(tmpref);
tmpref.offset:=spilltemp.offset;
tmpref.refaddr:=addr_hi;
helplist.concat(taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref));
ins:=taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref);
add_cpu_interferences(ins);
helplist.concat(ins);
tmpref:=spilltemp;
tmpref.refaddr:=addr_lo;
tmpref.base:=hreg;
helplist.concat(spilling_create_load(tmpref,tempreg));
ins:=spilling_create_load(tmpref,tempreg);
add_cpu_interferences(ins);
helplist.concat(ins);
if getregtype(tempreg)=R_INTREGISTER then
ungetregisterinline(helplist,hreg);
@ -101,6 +107,7 @@ unit rgcpu;
helplist : TAsmList;
l : tasmlabel;
hreg : tregister;
ins : Taicpu;
begin
if (spilltemp.offset<low(smallint)) or
(spilltemp.offset>high(smallint)) then
@ -113,18 +120,23 @@ unit rgcpu;
if getregtype(tempreg)=R_INTREGISTER then
begin
hreg:=getregisterinline(helplist,R_SUBWHOLE);
add_edge(getsupreg(hreg),RS_R0);
{Done by add_cpu_interferences now.
add_edge(getsupreg(hreg),RS_R0);}
end
else
hreg:=cg.getintregister(helplist,OS_ADDR);
reference_reset(tmpref);
tmpref.offset:=spilltemp.offset;
tmpref.refaddr:=addr_hi;
helplist.concat(taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref));
ins:=taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref);
add_cpu_interferences(ins);
helplist.concat(ins);
tmpref:=spilltemp;
tmpref.refaddr:=addr_lo;
tmpref.base:=hreg;
helplist.concat(spilling_create_store(tempreg,tmpref));
ins:=spilling_create_store(tempreg,tmpref);
add_cpu_interferences(ins);
helplist.concat(ins);
if getregtype(tempreg)=R_INTREGISTER then
ungetregisterinline(helplist,hreg);

22
compiler/rgobj.pas
View File

@ -1787,14 +1787,24 @@ unit rgobj;
procedure Trgobj.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
var ins:Taicpu;
begin
list.insertafter(spilling_create_load(spilltemp,tempreg),pos);
ins:=spilling_create_load(spilltemp,tempreg);
add_cpu_interferences(ins);
list.insertafter(ins,pos);
end;
procedure Trgobj.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
var ins:Taicpu;
begin
list.insertafter(spilling_create_store(tempreg,spilltemp),pos);
ins:=spilling_create_store(tempreg,spilltemp);
add_cpu_interferences(ins);
list.insertafter(ins,pos);
end;
@ -2048,8 +2058,7 @@ unit rgobj;
{ substitute registers }
for counter:=0 to instr.ops-1 do
with instr.oper[counter]^ do
begin
with instr.oper[counter]^ do
case typ of
top_reg:
begin
@ -2072,7 +2081,10 @@ unit rgobj;
end;
{$endif ARM}
end;
end;
{We have modified the instruction; perhaps the new instruction has
certain constraints regarding which imaginary registers interfere
with certain physical registers.}
add_cpu_interferences(instr);
end;
end.

8
compiler/sparc/aasmcpu.pas
View File

@ -75,8 +75,8 @@ uses
procedure InitAsm;
procedure DoneAsm;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
implementation
@ -259,7 +259,7 @@ implementation
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :
@ -281,7 +281,7 @@ implementation
end;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :

8
compiler/x86/aasmcpu.pas
View File

@ -262,8 +262,8 @@ interface
function FindInsentry(objdata:TObjData):boolean;
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
procedure InitAsm;
procedure DoneAsm;
@ -2366,7 +2366,7 @@ implementation
end;
function spilling_create_load(const ref:treference;r:tregister): tai;
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :
@ -2388,7 +2388,7 @@ implementation
end;
function spilling_create_store(r:tregister; const ref:treference): tai;
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
begin
case getregtype(r) of
R_INTREGISTER :