diff --git a/.gitattributes b/.gitattributes
index 6f3f82a43d..37435b6a0e 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -638,6 +638,7 @@ compiler/ppcmipsel.lpi svneol=native#text/plain
compiler/ppcppc.lpi svneol=native#text/plain
compiler/ppcppc64.lpi svneol=native#text/plain
compiler/ppcsparc.lpi svneol=native#text/plain
+compiler/ppcsparc64.lpi svneol=native#text/plain
compiler/ppheap.pas svneol=native#text/plain
compiler/ppu.pas svneol=native#text/plain
compiler/ppx86_64.lpi svneol=native#text/plain
@@ -694,6 +695,7 @@ compiler/sparc/rspsup.inc svneol=native#text/plain
compiler/sparc/spreg.dat svneol=native#text/plain
compiler/sparc/strinst.inc svneol=native#text/plain
compiler/sparc/symcpu.pas svneol=native#text/plain
+compiler/sparc64/cpuinfo.pas svneol=native#text/plain
compiler/switches.pas svneol=native#text/plain
compiler/symbase.pas svneol=native#text/plain
compiler/symconst.pas svneol=native#text/plain
diff --git a/compiler/Makefile.fpc b/compiler/Makefile.fpc
index 08b6b029d1..9f26b1c0c9 100644
--- a/compiler/Makefile.fpc
+++ b/compiler/Makefile.fpc
@@ -32,7 +32,7 @@ fpcdir=..
unexport FPC_VERSION FPC_COMPILERINFO
# Which platforms are ready for inclusion in the cycle
-CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64
+CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64
# All supported targets used for clean
ALLTARGETS=$(CYCLETARGETS)
@@ -47,6 +47,9 @@ endif
ifdef SPARC
PPC_TARGET=sparc
endif
+ifdef SPARC64
+PPC_TARGET=sparc64
+endif
ifdef M68K
PPC_TARGET=m68k
endif
@@ -182,6 +185,9 @@ endif
ifeq ($(CPC_TARGET),sparc)
CPUSUF=sparc
endif
+ifeq ($(CPC_TARGET),sparc64)
+CPUSUF=sparc64
+endif
ifeq ($(CPC_TARGET),x86_64)
CPUSUF=x64
endif
@@ -281,7 +287,12 @@ endif
# Sparc specific
ifeq ($(PPC_TARGET),sparc)
-override LOCALOPT+=
+override LOCALOPT+=-Fusparcgen
+endif
+
+# Sparc specific
+ifeq ($(PPC_TARGET),sparc64)
+override LOCALOPT+=-Fusparcgen
endif
# ARM specific
@@ -411,7 +422,7 @@ endif
# CPU targets
#####################################################################
-PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64
+PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64
INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
SYMLINKINSTALL_TARGETS=$(addsuffix _symlink_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
@@ -773,7 +784,7 @@ ifeq ($(OS_SOURCE),win64)
EXCLUDE_80BIT_TARGETS=1
endif
-ifneq ($(findstring $(CPU_SOURCE),aarch64 arm avr jvm m68k mips mipsel powerpc powerpc64 sparc),)
+ifneq ($(findstring $(CPU_SOURCE),aarch64 arm avr jvm m68k mips mipsel powerpc powerpc64 sparc sparc64),)
EXCLUDE_80BIT_TARGETS=1
endif
diff --git a/compiler/fpcdefs.inc b/compiler/fpcdefs.inc
index d3ba0528f6..a9eac01f18 100644
--- a/compiler/fpcdefs.inc
+++ b/compiler/fpcdefs.inc
@@ -102,8 +102,20 @@
{$define cputargethasfixedstack}
{$define cpurefshaveindexreg}
{$define SUPPORT_SAFECALL}
+ {$define sparcgen}
{$endif sparc}
+{$ifdef sparc64}
+ {$define cpu64bit}
+ {$define cpu64bitaddr}
+ {$define cpu64bitalu}
+ {$define cpuflags}
+ {$define cputargethasfixedstack}
+ {$define cpurefshaveindexreg}
+ {$define SUPPORT_SAFECALL}
+ {$define sparcgen}
+{$endif sparc64}
+
{$ifdef powerpc}
{$define cpu32bit}
{$define cpu32bitaddr}
diff --git a/compiler/globals.pas b/compiler/globals.pas
index 7e7026b048..b75e04589e 100644
--- a/compiler/globals.pas
+++ b/compiler/globals.pas
@@ -449,6 +449,12 @@ interface
asmcputype : cpu_none;
fputype : fpu_hard;
{$endif sparc}
+ {$ifdef sparc64}
+ cputype : cpu_SPARC_V9;
+ optimizecputype : cpu_SPARC_V9;
+ asmcputype : cpu_none;
+ fputype : fpu_hard;
+ {$endif sparc64}
{$ifdef arm}
cputype : cpu_armv4;
optimizecputype : cpu_armv4;
diff --git a/compiler/pp.pas b/compiler/pp.pas
index b3f7813083..afdf19d5d7 100644
--- a/compiler/pp.pas
+++ b/compiler/pp.pas
@@ -30,6 +30,7 @@ program pp;
x86_64 generate a compiler for the AMD x86-64 architecture
M68K generate a compiler for the M68000
SPARC generate a compiler for SPARC
+ SPARC64 generate a compiler for SPARC64
POWERPC generate a compiler for the PowerPC
POWERPC64 generate a compiler for the PowerPC64 architecture
DEBUG version with debug code is generated
@@ -104,6 +105,12 @@ program pp;
{$endif CPUDEFINED}
{$define CPUDEFINED}
{$endif SPARC}
+{$ifdef SPARC64}
+ {$ifdef CPUDEFINED}
+ {$fatal ONLY one of the switches for the CPU type must be defined}
+ {$endif CPUDEFINED}
+ {$define CPUDEFINED}
+{$endif SPARC64}
{$ifdef ARM}
{$ifdef CPUDEFINED}
{$fatal ONLY one of the switches for the CPU type must be defined}
diff --git a/compiler/ppcsparc.lpi b/compiler/ppcsparc.lpi
index a90dcc28a4..1ac62eee0c 100644
--- a/compiler/ppcsparc.lpi
+++ b/compiler/ppcsparc.lpi
@@ -1,7 +1,7 @@
-
+
-
+
@@ -32,12 +32,10 @@
-
-
@@ -48,8 +46,8 @@
-
-
+
+
@@ -70,7 +68,6 @@
-
diff --git a/compiler/ppcsparc64.lpi b/compiler/ppcsparc64.lpi
new file mode 100644
index 0000000000..3426a089cc
--- /dev/null
+++ b/compiler/ppcsparc64.lpi
@@ -0,0 +1,73 @@
+
+
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+
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+
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+
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+
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diff --git a/compiler/sparc64/cpuinfo.pas b/compiler/sparc64/cpuinfo.pas
new file mode 100644
index 0000000000..de54a3f1e9
--- /dev/null
+++ b/compiler/sparc64/cpuinfo.pas
@@ -0,0 +1,113 @@
+{
+ Copyright (c) 1998-2002 by Florian Klaempfl
+
+ Basic Processor information for the SPARC64
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit cpuinfo;
+
+{$i fpcdefs.inc}
+
+interface
+
+uses
+ globtype;
+
+type
+ bestreal = double;
+{$if FPC_FULLVERSION>20700}
+ bestrealrec = TDoubleRec;
+{$endif FPC_FULLVERSION>20700}
+ ts32real = single;
+ ts64real = double;
+ ts80real = extended;
+ ts128real = type extended;
+ ts64comp = type extended;
+ pbestreal=^bestreal;
+
+ { possible supported processors for this target }
+ tcputype=(cpu_none,
+ cpu_SPARC_V9
+ );
+
+ tfputype =(fpu_none,
+ fpu_soft,
+ fpu_hard
+ );
+
+ tcontrollertype =(ct_none
+ );
+
+ tcontrollerdatatype = record
+ controllertypestr, controllerunitstr: string[20];
+ cputype: tcputype; fputype: tfputype;
+ flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
+ end;
+
+
+Const
+ { Is there support for dealing with multiple microcontrollers available }
+ { for this platform? }
+ ControllerSupport = true;
+
+ { We know that there are fields after sramsize
+ but we don't care about this warning }
+ {$PUSH}
+ {$WARN 3177 OFF}
+ embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
+ (
+ (controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
+ {$POP}
+
+ { calling conventions supported by the code generator }
+ supported_calling_conventions : tproccalloptions = [
+ pocall_internproc,
+ pocall_stdcall,
+ pocall_safecall,
+ pocall_cdecl,
+ pocall_cppdecl
+ ];
+
+ cputypestr : array[tcputype] of string[10] = ('',
+ 'SPARCV9'
+ );
+
+ fputypestr : array[tfputype] of string[6] = ('',
+ 'SOFT',
+ 'HARD'
+ );
+
+ { Supported optimizations, only used for information }
+ supported_optimizerswitches = genericlevel1optimizerswitches+
+ genericlevel2optimizerswitches+
+ genericlevel3optimizerswitches-
+ { no need to write info about those }
+ [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
+ [cs_opt_regvar,cs_opt_loopunroll,
+ cs_opt_tailrecursion,cs_opt_nodecse,
+ cs_opt_reorder_fields,cs_opt_fastmath];
+
+ level1optimizerswitches = genericlevel1optimizerswitches;
+ level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
+ [cs_opt_regvar,cs_opt_tailrecursion,cs_opt_nodecse];
+ level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
+ level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
+
+implementation
+
+end.