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* replace several emit_const_reg calls that generate SHR or SAR instructions

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with calls to cg.a_op_const_reg in the x86 div code generator, so that the
  same code can be used in the future for i8086 as well (SHR and SAR by
  constants other than 1 are 186+, so on 8086 they have to go through the CL
  register, which is handled correctly in cg.a_op_const_reg)

git-svn-id: trunk@36815 -
This commit is contained in:
nickysn 2017-07-31 16:02:52 +00:00
parent f4718c0969
commit 19087d04da
1 changed files with 4 additions and 4 deletions
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8
compiler/x86/nx86mat.pas
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@ -424,12 +424,12 @@ interface
if tordconstnode(right).value=2 then
begin
{If the left value is negative, hreg2=(right value-1)=1, otherwise 0.}
emit_const_reg(A_SHR,opsize,resultdef.size*8-1,hreg2);
cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,cgsize,resultdef.size*8-1,hreg2);
end
else
begin
{If the left value is negative, hreg2=$ffffffff, otherwise 0.}
emit_const_reg(A_SAR,opsize,resultdef.size*8-1,hreg2);
cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,cgsize,resultdef.size*8-1,hreg2);
{If negative, hreg2=right value-1, otherwise 0.}
{ (don't use emit_const_reg, because if value>high(longint)
then it must first be loaded into a register) }
@ -438,10 +438,10 @@ interface
{ add to the left value }
emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
{ do the shift }
emit_const_reg(A_SAR,opsize,power,hreg1);
cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,cgsize,power,hreg1);
end
else
emit_const_reg(A_SHR,opsize,power,hreg1);
cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,cgsize,power,hreg1);
location.register:=hreg1;
end
else