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implemented OP_SHL, OP_SHR and OP_SAR in tcg8086.a_op_reg_reg

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git-svn-id: branches/i8086@23751 -
This commit is contained in:
nickysn 2013-03-09 17:14:00 +00:00
parent 588b12200b
commit 1937ef8300
1 changed files with 47 additions and 0 deletions
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47
compiler/i8086/cgcpu.pas
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@ -150,9 +150,13 @@ unit cgcpu;
src, dst: TRegister);
var
op1, op2: TAsmOp;
hl_skip, hl_loop_start: TAsmLabel;
ai: taicpu;
begin
check_register_size(size,src);
check_register_size(size,dst);
if size in [OS_64, OS_S64] then
internalerror(2013030902);
if size in [OS_32, OS_S32] then
begin
case op of
@ -177,6 +181,49 @@ unit cgcpu;
list.concat(taicpu.op_reg_reg(op1, S_W, src, dst));
list.concat(taicpu.op_reg_reg(op2, S_W, GetNextReg(src), GetNextReg(dst)));
end;
OP_SHR,OP_SHL,OP_SAR:
begin
getcpuregister(list,NR_CX);
a_load_reg_reg(list,size,OS_16,src,NR_CX);
list.concat(taicpu.op_const_reg(A_AND,S_W,$1f,NR_CX));
current_asmdata.getjumplabel(hl_skip);
ai:=Taicpu.Op_Sym(A_Jcc,S_NO,hl_skip);
ai.SetCondition(C_Z);
ai.is_jmp:=true;
list.concat(ai);
current_asmdata.getjumplabel(hl_loop_start);
a_label(list,hl_loop_start);
case op of
OP_SHR:
begin
list.concat(taicpu.op_const_reg(A_SHR,S_W,1,GetNextReg(dst)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,dst));
end;
OP_SAR:
begin
list.concat(taicpu.op_const_reg(A_SAR,S_W,1,GetNextReg(dst)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,dst));
end;
OP_SHL:
begin
list.concat(taicpu.op_const_reg(A_SHL,S_W,1,dst));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(dst)));
end;
else
internalerror(2013030903);
end;
ai:=Taicpu.Op_Sym(A_LOOP,S_W,hl_loop_start);
ai.is_jmp:=true;
list.concat(ai);
a_label(list,hl_skip);
ungetcpuregister(list,NR_CX);
end;
else
internalerror(2013030901);
end;