From 1add3490c326215fb09024fa987c80435c1c1b6c Mon Sep 17 00:00:00 2001 From: florian Date: Wed, 4 Nov 2020 22:10:35 +0000 Subject: [PATCH] + i386 supports also avx-512 git-svn-id: trunk@47317 - --- compiler/i386/cpuinfo.pas | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/compiler/i386/cpuinfo.pas b/compiler/i386/cpuinfo.pas index 8e4cbc9595..b6a0e7fcd5 100644 --- a/compiler/i386/cpuinfo.pas +++ b/compiler/i386/cpuinfo.pas @@ -67,7 +67,8 @@ Type fpu_sse41, fpu_sse42, fpu_avx, - fpu_avx2 + fpu_avx2, + fpu_avx512f ); tcontrollertype = @@ -122,7 +123,7 @@ Const 'COREAVX2' ); - fputypestr : array[tfputype] of string[6] = ( + fputypestr : array[tfputype] of string[7] = ( 'NONE', // 'SOFT', 'X87', @@ -133,13 +134,14 @@ Const 'SSE41', 'SSE42', 'AVX', - 'AVX2' + 'AVX2', + 'AVX512F' ); - sse_singlescalar = [fpu_sse..fpu_avx2]; - sse_doublescalar = [fpu_sse2..fpu_avx2]; + sse_singlescalar = [fpu_sse..fpu_avx512f]; + sse_doublescalar = [fpu_sse2..fpu_avx512f]; - fpu_avx_instructionsets = [fpu_avx,fpu_avx2]; + fpu_avx_instructionsets = [fpu_avx,fpu_avx2,fpu_avx512f]; { Supported optimizations, only used for information } supported_optimizerswitches = genericlevel1optimizerswitches+ @@ -174,7 +176,8 @@ type tfpuflags = (FPUX86_HAS_AVXUNIT, - FPUX86_HAS_32MMREGS + FPUX86_HAS_32MMREGS, + FPUX86_HAS_AVX512F ); const @@ -202,7 +205,8 @@ type { fpu_sse41 } [], { fpu_sse42 } [], { fpu_avx } [FPUX86_HAS_AVXUNIT], - { fpu_avx2 } [FPUX86_HAS_AVXUNIT] + { fpu_avx2 } [FPUX86_HAS_AVXUNIT], + { fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_32MMREGS,FPUX86_HAS_AVX512F] ); Implementation