paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-04-08 07:08:12 +02:00
Code Issues Packages Projects Releases Wiki Activity

+ xtensa: make use of float.s instruction

Browse Source 
git-svn-id: trunk@46962 -
This commit is contained in:
florian 2020-09-26 20:12:29 +00:00
parent 4ced513363
commit 1c370ccde1
1 changed files with 40 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
compiler/xtensa/ncpucnv.pas
View File

@ -33,6 +33,8 @@ interface
protected
function first_real_to_real: tnode;override;
procedure second_int_to_bool;override;
procedure second_int_to_real;override;
function first_int_to_real: tnode;override;
end;
implementation
@ -67,7 +69,7 @@ implementation
left:=nil;
end;
else
internalerror(200610151);
internalerror(2020092603);
end;
s64real:
case tfloatdef(resultdef).floattype of
@ -80,10 +82,10 @@ implementation
left:=nil;
end;
else
internalerror(200610152);
internalerror(2020092602);
end;
else
internalerror(200610153);
internalerror(2020092601);
end;
left:=nil;
firstpass(result);
@ -94,7 +96,6 @@ implementation
end;
procedure tcputypeconvnode.second_int_to_bool;
var
hreg1, onereg: tregister;
@ -187,6 +188,41 @@ implementation
end;
function tcputypeconvnode.first_int_to_real: tnode;
var
fname: string[19];
begin
if (cs_fp_emulation in current_settings.moduleswitches) or
(current_settings.fputype=fpu_soft) or
not(FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) or
((is_double(resultdef)) and not(FPUXTENSA_DOUBLE in fpu_capabilities[current_settings.fputype])) or
is_64bitint(left.resultdef) or
is_currency(left.resultdef) or
(is_32bit(left.resultdef) and not(is_signed(left.resultdef))) then
result:=inherited first_int_to_real
else
begin
{ other integers are supposed to be 32 bit }
inserttypeconv(left,s32inttype);
firstpass(left);
result:=nil;
expectloc:=LOC_FPUREGISTER;
end;
end;
procedure tcputypeconvnode.second_int_to_real;
var
ai: taicpu;
begin
location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,s32inttype,true);
ai:=taicpu.op_reg_reg_const(A_FLOAT,location.register,left.location.register,0);
ai.oppostfix:=PF_S;
current_asmdata.CurrAsmList.concat(ai);
end;
begin
ctypeconvnode:=tcputypeconvnode;
end.