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* x86: Reversal of DoAddRefOpt optimisation if no pipeline saving is made
This commit is contained in:
J. Gareth "Curious Kit" Moreton
parent
45883c2cc0
commit
1d86db3100
@ -157,6 +157,7 @@ unit aoptx86;
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function DoArithCombineOpt(var p : tai) : Boolean;
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function DoAddRefOpt(var p, hp1: tai; Reg: TRegister; Value: TCGInt): Boolean;
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function DoReverseAddRefOpt(var p: tai; Value: TCGInt): Boolean;
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function DoMovCmpMemOpt(var p : tai; const hp1: tai) : Boolean;
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function DoSETccLblRETOpt(var p: tai; const hp_label: tai_label) : Boolean;
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@ -6449,6 +6450,73 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.DoReverseAddRefOpt(var p: tai; Value: TCGInt): Boolean;
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var
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CurrentRef: PReference;
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OtherRegister: TRegister;
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X: Integer;
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hp1, hp2: tai;
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begin
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{ Assume that p has been checked and confirmed to be of the form
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"ADD/SUB const,%reg" }
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Result := False;
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if GetLastInstruction(p, hp1) and (hp1.typ = ait_instruction) and
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{ Make sure this instruction doesn't also modify the register used in
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the ADD/SUB instruction }
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not RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp1) then
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begin
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{ Find the reference }
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for X := 0 to taicpu(Hp1).ops - 1 do
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if (taicpu(hp1).oper[X]^.typ = top_ref) then
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begin
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{ Locally store the pointer to the reference }
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CurrentRef := taicpu(hp1).oper[X]^.ref;
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if
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{ Only references of the form x(%reg1,%reg2,scale) can be
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optimised here }
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(CurrentRef^.refaddr <> addr_no) or
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not RegInRef(taicpu(p).oper[1]^.reg, CurrentRef^) then
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Exit;
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{ Account for the scale factor on the value }
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if SuperRegistersEqual(taicpu(p).oper[1]^.reg, CurrentRef^.index) then
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begin
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OtherRegister := CurrentRef^.base;
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if SuperRegistersEqual(taicpu(p).oper[1]^.reg, CurrentRef^.base) then
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Inc(Value, Value * max(CurrentRef^.scalefactor, 1))
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else
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Value := Value * max(CurrentRef^.scalefactor, 1);
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end
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else
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OtherRegister := CurrentRef^.index;
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if (OtherRegister <> NR_NO) and
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{ If we can't set the offset to zero, this is wasted effort }
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(CurrentRef^.offset = Value)
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and GetLastInstruction(hp1, hp2) and
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{ Make sure there is a pipeline stall between hp2 and hp1,
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otherwise a saving won't be made }
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RegModifiedByInstruction(OtherRegister, hp2) then
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begin
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taicpu(hp1).oper[X]^.ref^.offset := 0;
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AsmL.Remove(hp1);
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AsmL.InsertAfter(hp1, p);
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{ In case OtherRegister got deallocated right after the reference }
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AllocRegBetween(OtherRegister, hp2, hp1, UsedRegs);
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DebugMsg(SPeepholeOptimization + 'Rearranged MOV; (ref); ADD/SUB to MOV; ADD/SUB; (ref) to remove offset and minimise cache pollution', hp2);
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{ Keep p as the current instruction }
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Result := True;
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end;
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end;
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end;
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end;
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function TX86AsmOptimizer.DoArithCombineOpt(var p: tai): Boolean;
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var
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hp1 : tai;
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@ -15495,131 +15563,145 @@ unit aoptx86;
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begin
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Result := False;
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{ Change:
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add/sub 128,(dest)
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To:
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sub/add -128,(dest)
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This generaally takes fewer bytes to encode because -128 can be stored
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in a signed byte, whereas +128 cannot.
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}
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if (taicpu(p).opsize <> S_B) and MatchOperand(taicpu(p).oper[0]^, 128) then
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if taicpu(p).oper[0]^.typ = top_const then
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begin
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if taicpu(p).opcode = A_ADD then
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Opposite := A_SUB
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else
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Opposite := A_ADD;
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{ Be careful if the flags are in use, because the CF flag inverts
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when changing from ADD to SUB and vice versa }
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if RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
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GetNextInstruction(p, hp1) then
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{ Sometimes, DoAddRefOpt makes an optimisation that doesn't
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improve code speed and only increases cache pollution. If these
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aren't cleared by other optimisations, rectify it here }
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if taicpu(p).oper[1]^.typ = top_reg then
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begin
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TransferUsedRegs(TmpUsedRegs);
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TmpUsedRegs[R_SPECIALREGISTER].Update(tai(p.Next), True);
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hp2 := hp1;
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{ Scan ahead to check if everything's safe }
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while Assigned(hp1) and RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) do
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begin
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if (hp1.typ <> ait_instruction) then
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{ Probably unsafe since the flags are still in use }
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Exit;
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if MatchInstruction(hp1, A_CALL, A_JMP, A_RET, []) then
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{ Stop searching at an unconditional jump }
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Break;
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if not
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(
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MatchInstruction(hp1, A_ADC, A_SBB, []) and
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(taicpu(hp1).oper[0]^.typ = top_const) { We need to be able to invert a constant }
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) and
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(taicpu(hp1).condition = C_None) and RegInInstruction(NR_DEFAULTFLAGS, hp1) then
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{ Instruction depends on FLAGS (and is not ADC or SBB); break out }
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Exit;
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UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
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TmpUsedRegs[R_SPECIALREGISTER].Update(tai(hp1.Next), True);
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{ Move to the next instruction }
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GetNextInstruction(hp1, hp1);
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end;
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while Assigned(hp2) and (hp2 <> hp1) do
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begin
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NewCond := C_None;
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case taicpu(hp2).condition of
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C_A, C_NBE:
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NewCond := C_BE;
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C_B, C_C, C_NAE:
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NewCond := C_AE;
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C_AE, C_NB, C_NC:
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NewCond := C_B;
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C_BE, C_NA:
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NewCond := C_A;
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else
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{ No change needed };
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end;
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if NewCond <> C_None then
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begin
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DebugMsg(SPeepholeOptimization + 'Condition changed from ' + cond2str[taicpu(hp2).condition] + ' to ' + cond2str[NewCond] +
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' to accommodate ' + debug_op2str(taicpu(p).opcode) + ' -> ' + debug_op2str(opposite) + ' above', hp2);
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taicpu(hp2).condition := NewCond;
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end
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else
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if MatchInstruction(hp2, A_ADC, A_SBB, []) then
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begin
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{ Because of the flipping of the carry bit, to ensure
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the operation remains equivalent, ADC becomes SBB
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and vice versa, and the constant is not-inverted.
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If multiple ADCs or SBBs appear in a row, each one
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changed causes the carry bit to invert, so they all
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need to be flipped }
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if taicpu(hp2).opcode = A_ADC then
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SecondOpposite := A_SBB
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else
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SecondOpposite := A_ADC;
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if taicpu(hp2).oper[0]^.typ <> top_const then
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{ Should have broken out of this optimisation already }
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InternalError(2021112901);
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DebugMsg(SPeepholeOptimization + debug_op2str(taicpu(hp2).opcode) + debug_opsize2str(taicpu(hp2).opsize) + ' $' + debug_tostr(taicpu(hp2).oper[0]^.val) + ',' + debug_operstr(taicpu(hp2).oper[1]^) + ' -> ' +
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debug_op2str(SecondOpposite) + debug_opsize2str(taicpu(hp2).opsize) + ' $' + debug_tostr(not taicpu(hp2).oper[0]^.val) + ',' + debug_operstr(taicpu(hp2).oper[1]^) + ' to accommodate inverted carry bit', hp2);
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{ Bit-invert the constant (effectively equivalent to "-1 - val") }
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taicpu(hp2).opcode := SecondOpposite;
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taicpu(hp2).oper[0]^.val := not taicpu(hp2).oper[0]^.val;
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end;
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{ Move to the next instruction }
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GetNextInstruction(hp2, hp2);
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end;
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if (hp2 <> hp1) then
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InternalError(2021111501);
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if taicpu(p).opcode = A_ADD then
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Result := DoReverseAddRefOpt(p, taicpu(p).oper[0]^.val)
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else
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Result := DoReverseAddRefOpt(p, -taicpu(p).oper[0]^.val);
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end;
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DebugMsg(SPeepholeOptimization + debug_op2str(taicpu(p).opcode) + debug_opsize2str(taicpu(p).opsize) + ' $128,' + debug_operstr(taicpu(p).oper[1]^) + ' changed to ' +
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debug_op2str(opposite) + debug_opsize2str(taicpu(p).opsize) + ' $-128,' + debug_operstr(taicpu(p).oper[1]^) + ' to reduce instruction size', p);
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{ Change:
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add/sub 128,(dest)
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taicpu(p).opcode := Opposite;
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taicpu(p).oper[0]^.val := -128;
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To:
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sub/add -128,(dest)
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{ No further optimisations can be made on this instruction, so move
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onto the next one to save time }
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p := tai(p.Next);
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UpdateUsedRegs(p);
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This generaally takes fewer bytes to encode because -128 can be stored
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in a signed byte, whereas +128 cannot.
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}
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if (taicpu(p).opsize <> S_B) and (taicpu(p).oper[0]^.val = 128) then
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begin
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if taicpu(p).opcode = A_ADD then
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Opposite := A_SUB
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else
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Opposite := A_ADD;
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Result := True;
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Exit;
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{ Be careful if the flags are in use, because the CF flag inverts
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when changing from ADD to SUB and vice versa }
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if RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
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GetNextInstruction(p, hp1) then
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begin
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TransferUsedRegs(TmpUsedRegs);
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TmpUsedRegs[R_SPECIALREGISTER].Update(tai(p.Next), True);
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hp2 := hp1;
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{ Scan ahead to check if everything's safe }
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while Assigned(hp1) and RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) do
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begin
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if (hp1.typ <> ait_instruction) then
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{ Probably unsafe since the flags are still in use }
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Exit;
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if MatchInstruction(hp1, A_CALL, A_JMP, A_RET, []) then
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{ Stop searching at an unconditional jump }
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Break;
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if not
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(
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MatchInstruction(hp1, A_ADC, A_SBB, []) and
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(taicpu(hp1).oper[0]^.typ = top_const) { We need to be able to invert a constant }
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) and
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(taicpu(hp1).condition = C_None) and RegInInstruction(NR_DEFAULTFLAGS, hp1) then
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{ Instruction depends on FLAGS (and is not ADC or SBB); break out }
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Exit;
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UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
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TmpUsedRegs[R_SPECIALREGISTER].Update(tai(hp1.Next), True);
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{ Move to the next instruction }
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GetNextInstruction(hp1, hp1);
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end;
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while Assigned(hp2) and (hp2 <> hp1) do
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begin
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NewCond := C_None;
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case taicpu(hp2).condition of
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C_A, C_NBE:
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NewCond := C_BE;
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C_B, C_C, C_NAE:
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NewCond := C_AE;
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C_AE, C_NB, C_NC:
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NewCond := C_B;
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C_BE, C_NA:
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NewCond := C_A;
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else
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{ No change needed };
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end;
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if NewCond <> C_None then
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begin
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DebugMsg(SPeepholeOptimization + 'Condition changed from ' + cond2str[taicpu(hp2).condition] + ' to ' + cond2str[NewCond] +
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' to accommodate ' + debug_op2str(taicpu(p).opcode) + ' -> ' + debug_op2str(opposite) + ' above', hp2);
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taicpu(hp2).condition := NewCond;
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end
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else
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if MatchInstruction(hp2, A_ADC, A_SBB, []) then
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begin
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{ Because of the flipping of the carry bit, to ensure
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the operation remains equivalent, ADC becomes SBB
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and vice versa, and the constant is not-inverted.
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If multiple ADCs or SBBs appear in a row, each one
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changed causes the carry bit to invert, so they all
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need to be flipped }
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if taicpu(hp2).opcode = A_ADC then
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SecondOpposite := A_SBB
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else
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SecondOpposite := A_ADC;
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if taicpu(hp2).oper[0]^.typ <> top_const then
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{ Should have broken out of this optimisation already }
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InternalError(2021112901);
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DebugMsg(SPeepholeOptimization + debug_op2str(taicpu(hp2).opcode) + debug_opsize2str(taicpu(hp2).opsize) + ' $' + debug_tostr(taicpu(hp2).oper[0]^.val) + ',' + debug_operstr(taicpu(hp2).oper[1]^) + ' -> ' +
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debug_op2str(SecondOpposite) + debug_opsize2str(taicpu(hp2).opsize) + ' $' + debug_tostr(not taicpu(hp2).oper[0]^.val) + ',' + debug_operstr(taicpu(hp2).oper[1]^) + ' to accommodate inverted carry bit', hp2);
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{ Bit-invert the constant (effectively equivalent to "-1 - val") }
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taicpu(hp2).opcode := SecondOpposite;
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taicpu(hp2).oper[0]^.val := not taicpu(hp2).oper[0]^.val;
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end;
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{ Move to the next instruction }
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GetNextInstruction(hp2, hp2);
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end;
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if (hp2 <> hp1) then
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InternalError(2021111501);
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end;
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DebugMsg(SPeepholeOptimization + debug_op2str(taicpu(p).opcode) + debug_opsize2str(taicpu(p).opsize) + ' $128,' + debug_operstr(taicpu(p).oper[1]^) + ' changed to ' +
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debug_op2str(opposite) + debug_opsize2str(taicpu(p).opsize) + ' $-128,' + debug_operstr(taicpu(p).oper[1]^) + ' to reduce instruction size', p);
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taicpu(p).opcode := Opposite;
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taicpu(p).oper[0]^.val := -128;
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{ No further optimisations can be made on this instruction, so move
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onto the next one to save time }
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p := tai(p.Next);
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UpdateUsedRegs(p);
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Result := True;
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Exit;
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end;
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end;
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{ Detect:
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