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* huge m68k/cgcpu.pas cleanup and improvement commit
- removed the ancient DEBUG_CHARLIE silliness... :) - moved some repeated code patterns into separate functions - rewrote most of of tcg68k.a_op_const_reg and tcg68k.a_op_reg_reg - smarter code generation in tcg68k.a_cmp_const_reg_label - added support for MULU/MULS on Coldfire in a case which is often used by the CG to index arrays to be used instead of the RTL helpers, this results in a *HUGE* speedup in tw5086 for example git-svn-id: trunk@25702 -
This commit is contained in:
Károly Balogh
parent
834008818f
commit
1f11c39a5d
@ -19,11 +19,7 @@
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****************************************************************************
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}
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{DEFINE DEBUG_CHARLIE}
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{$IFNDEF DEBUG_CHARLIE}
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{$WARNINGS OFF}
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{$ENDIF}
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unit cgcpu;
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{$i fpcdefs.inc}
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@ -110,6 +106,8 @@ unit cgcpu;
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}
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procedure sign_extend(list: TAsmList;_oldsize : tcgsize; reg: tregister);
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procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
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function force_to_dataregister(list: TAsmList; size: TCGSize; reg: TRegister): TRegister;
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procedure move_if_needed(list: TAsmList; size: TCGSize; src: TRegister; dest: TRegister);
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end;
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@ -240,9 +238,6 @@ unit cgcpu;
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pushsize : tcgsize;
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ref : treference;
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begin
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_load_reg');_cgpara
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{$endif DEBUG_CHARLIE}
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{ it's probably necessary to port this from x86 later, or provide an m68k solution (KB) }
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{ TODO: FIX ME! check_register_size()}
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// check_register_size(size,r);
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@ -268,9 +263,6 @@ unit cgcpu;
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pushsize : tcgsize;
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ref : treference;
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begin
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_load_const');_cgpara
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{$endif DEBUG_CHARLIE}
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if use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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@ -337,10 +329,6 @@ unit cgcpu;
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len : tcgint;
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href : treference;
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begin
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_load_ref');_cgpara
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{$endif DEBUG_CHARLIE}
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{ cgpara.size=OS_NO requires a copy on the stack }
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if use_push(cgpara) then
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begin
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@ -372,9 +360,6 @@ unit cgcpu;
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tmpreg : tregister;
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opsize : topsize;
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begin
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_loadaddr_ref');_cgpara
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{$endif DEBUG_CHARLIE}
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with r do
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begin
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{ i suppose this is not required for m68k (KB) }
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@ -690,9 +675,6 @@ unit cgcpu;
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tmpreg : tregister;
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instr : taicpu;
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begin
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{$ifdef DEBUG_CHARLIE}
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list.concat(tai_comment.create(strpnew('a_call_reg')));
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{$endif}
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if isaddressregister(reg) then
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begin
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{ if we have an address register, we can jump to the address directly }
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@ -714,10 +696,6 @@ unit cgcpu;
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procedure tcg68k.a_load_const_reg(list : TAsmList;size : tcgsize;a : tcgint;register : tregister);
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begin
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_load_const_reg');
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{$endif DEBUG_CHARLIE}
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if isaddressregister(register) then
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begin
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list.concat(taicpu.op_const_reg(A_MOVE,S_L,longint(a),register))
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@ -749,10 +727,6 @@ unit cgcpu;
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hreg : tregister;
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href : treference;
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begin
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{$ifdef DEBUG_CHARLIE}
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list.concat(tai_comment.create(strpnew('a_load_const_ref')));
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{$endif DEBUG_CHARLIE}
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href:=ref;
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fixref(list,href);
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{ for coldfire we need to go through a temporary register if we have a
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@ -781,9 +755,6 @@ unit cgcpu;
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begin
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href := ref;
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fixref(list,href);
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{$ifdef DEBUG_CHARLIE}
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list.concat(tai_comment.create(strpnew('a_load_reg_ref')));
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{$endif DEBUG_CHARLIE}
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if tcgsize2size[fromsize]<tcgsize2size[tosize] then
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size:=fromsize
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else
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@ -805,10 +776,7 @@ unit cgcpu;
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bref := dref;
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fixref(list,aref);
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fixref(list,bref);
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{$ifdef DEBUG_CHARLIE}
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// writeln('a_load_ref_ref');
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{$endif DEBUG_CHARLIE}
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if fromsize<>tosize then
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if TCGSize2OpSize[fromsize]<>TCGSize2OpSize[tosize] then
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begin
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{ if we need to change the size then always use a temporary
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register }
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@ -1041,139 +1009,92 @@ unit cgcpu;
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{ Optimized, replaced with a simple load }
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a_load_const_reg(list,size,a,reg);
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end;
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OP_ADD :
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OP_ADD,
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OP_SUB:
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begin
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if (a >= 1) and (a <= 8) then
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list.concat(taicpu.op_const_reg(A_ADDQ,S_L,a, reg))
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else
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begin
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{ all others, including coldfire }
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list.concat(taicpu.op_const_reg(A_ADD,S_L,a, reg));
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end;
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{ add/sub works the same way, so have it unified here }
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if (a >= 1) and (a <= 8) and not isaddressregister(reg) then
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if (op = OP_ADD) then
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opcode:=A_ADDQ
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else
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opcode:=A_SUBQ;
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list.concat(taicpu.op_const_reg(opcode, S_L, a, reg));
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end;
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OP_AND,
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OP_OR:
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OP_OR,
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OP_XOR:
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begin
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if isaddressregister(reg) then
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scratch_reg := force_to_dataregister(list, size, reg);
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list.concat(taicpu.op_const_reg(opcode, S_L, a, scratch_reg));
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move_if_needed(list, size, scratch_reg, reg);
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end;
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OP_DIV,
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OP_IDIV:
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begin
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internalerror(20020816);
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end;
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OP_MUL,
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OP_IMUL:
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begin
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{ NOTE: better have this as fast as possible on every CPU in all cases,
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because the compiler uses OP_IMUL for array indexing... (KB) }
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{ ColdFire doesn't support MULS/MULU <imm>,dX }
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if current_settings.cputype in cpu_coldfire then
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begin
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{ use scratch register (there is a anda/ora though...) }
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scratch_reg:=getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg,scratch_reg);
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add_move_instruction(instr);
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list.concat(instr);
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list.concat(taicpu.op_const_reg(opcode,S_L,longint(a),scratch_reg));
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg);
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add_move_instruction(instr);
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list.concat(instr);
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{ move const to a register first }
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scratch_reg := getintregister(list,OS_INT);
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a_load_const_reg(list, size, a, scratch_reg);
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{ do the multiplication }
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scratch_reg2 := force_to_dataregister(list, size, reg);
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sign_extend(list, size, scratch_reg2);
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list.concat(taicpu.op_reg_reg(opcode,S_L,scratch_reg,scratch_reg2));
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{ move the value back to the original register }
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move_if_needed(list, size, scratch_reg2, reg);
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end
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else
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list.concat(taicpu.op_const_reg(topcg2tasmop[op],S_L,longint(a), reg));
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end;
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OP_DIV :
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begin
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internalerror(20020816);
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end;
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OP_IDIV :
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begin
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internalerror(20020816);
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end;
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OP_IMUL :
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begin
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if current_settings.cputype<>cpu_MC68020 then
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call_rtl_mul_const_reg(list,size,a,reg,'fpc_mul_longint')
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else
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begin
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if (isaddressregister(reg)) then
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begin
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scratch_reg := getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg);
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add_move_instruction(instr);
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list.concat(instr);
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list.concat(taicpu.op_const_reg(A_MULS,S_L,a,scratch_reg));
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg);
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add_move_instruction(instr);
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list.concat(instr);
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end
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begin
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if current_settings.cputype = cpu_mc68020 then
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begin
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{ do the multiplication }
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scratch_reg := force_to_dataregister(list, size, reg);
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sign_extend(list, size, scratch_reg);
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list.concat(taicpu.op_const_reg(opcode,S_L,a,scratch_reg));
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{ move the value back to the original register }
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move_if_needed(list, size, scratch_reg, reg);
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end
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else
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{ Fallback branch, plain 68000 for now }
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{ FIX ME: this is slow as hell, but original 68000 doesn't have 32x32 -> 32bit MUL (KB) }
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if op = OP_MUL then
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call_rtl_mul_const_reg(list, size, a, reg,'fpc_mul_dword')
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else
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list.concat(taicpu.op_const_reg(A_MULS,S_L,a,reg));
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end;
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end;
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OP_MUL :
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begin
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if current_settings.cputype<>cpu_MC68020 then
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call_rtl_mul_const_reg(list,size,a,reg,'fpc_mul_dword')
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else
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begin
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if (isaddressregister(reg)) then
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begin
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scratch_reg := getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg);
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add_move_instruction(instr);
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list.concat(instr);
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list.concat(taicpu.op_const_reg(A_MULU,S_L,a,scratch_reg));
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg);
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add_move_instruction(instr);
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list.concat(instr);
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end
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else
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list.concat(taicpu.op_const_reg(A_MULU,S_L,a,reg));
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end;
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call_rtl_mul_const_reg(list, size, a, reg,'fpc_mul_longint');
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end;
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end;
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OP_SAR,
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OP_SHL,
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OP_SHR :
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begin
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scratch_reg := force_to_dataregister(list, size, reg);
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sign_extend(list, size, scratch_reg);
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if (a >= 1) and (a <= 8) then
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begin
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{ not allowed to shift an address register }
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if (isaddressregister(reg)) then
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begin
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scratch_reg := getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg);
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add_move_instruction(instr);
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list.concat(instr);
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list.concat(taicpu.op_const_reg(opcode,S_L,a, scratch_reg));
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg,reg);
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add_move_instruction(instr);
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list.concat(instr);
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end
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else
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list.concat(taicpu.op_const_reg(opcode,S_L,a, reg));
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end
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else
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begin
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{ we must load the data into a register ... :() }
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scratch_reg := cg.getintregister(list,OS_INT);
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list.concat(taicpu.op_const_reg(A_MOVE,S_L,a, scratch_reg));
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{ again... since shifting with address register is not allowed }
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if (isaddressregister(reg)) then
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begin
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scratch_reg2 := cg.getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg, scratch_reg2);
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add_move_instruction(instr);
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list.concat(instr);
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list.concat(taicpu.op_reg_reg(opcode,S_L,scratch_reg, scratch_reg2));
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,scratch_reg2,reg);
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add_move_instruction(instr);
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list.concat(instr);
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end
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else
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list.concat(taicpu.op_reg_reg(opcode,S_L,scratch_reg, reg));
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end;
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end;
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OP_SUB :
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begin
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if (a >= 1) and (a <= 8) then
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list.concat(taicpu.op_const_reg(A_SUBQ,S_L,a,reg))
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begin
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list.concat(taicpu.op_const_reg(opcode, S_L, a, scratch_reg));
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end
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else
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begin
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{ all others, including coldfire }
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list.concat(taicpu.op_const_reg(A_SUB,S_L,a, reg));
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{ move const to a register first }
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scratch_reg2 := getintregister(list,OS_INT);
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a_load_const_reg(list, size, a, scratch_reg2);
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{ do the operation }
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list.concat(taicpu.op_reg_reg(opcode, S_L, scratch_reg2, scratch_reg));
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end;
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end;
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OP_XOR :
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begin
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list.concat(taicpu.op_const_reg(A_EORI,S_L,a, reg));
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{ move the value back to the original register }
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move_if_needed(list, size, scratch_reg, reg);
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end;
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else
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internalerror(20020729);
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@ -1209,51 +1130,38 @@ unit cgcpu;
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procedure tcg68k.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; reg1, reg2: TRegister);
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var
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hreg1,hreg2,r,r2: tregister;
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instr : taicpu;
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paraloc1,paraloc2,paraloc3 : tcgpara;
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hreg1, hreg2,r,r2: tregister;
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instr : taicpu;
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opcode : tasmop;
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opsize : topsize;
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begin
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opcode := topcg2tasmop[op];
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if current_settings.cputype in cpu_coldfire then
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opsize := S_L
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else
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opsize := TCGSize2OpSize[size];
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case op of
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OP_ADD :
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OP_ADD,
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OP_SUB:
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begin
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if current_settings.cputype in cpu_ColdFire then
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if current_settings.cputype in cpu_coldfire then
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begin
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{ operation only allowed only a longword }
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sign_extend(list, size, reg1);
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sign_extend(list, size, reg2);
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list.concat(taicpu.op_reg_reg(A_ADD,S_L,reg1, reg2));
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end
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else
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begin
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list.concat(taicpu.op_reg_reg(A_ADD,TCGSize2OpSize[size],reg1, reg2));
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end;
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list.concat(taicpu.op_reg_reg(opcode, opsize, reg1, reg2));
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end;
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OP_AND,OP_OR,
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OP_SAR,OP_SHL,
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OP_SHR,OP_SUB,OP_XOR :
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OP_SHR,OP_XOR:
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begin
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{ load to data registers }
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if (isaddressregister(reg1)) then
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begin
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hreg1 := getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1);
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add_move_instruction(instr);
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list.concat(instr);
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end
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else
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hreg1 := reg1;
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{ load to data registers }
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hreg1 := force_to_dataregister(list, size, reg1);
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hreg2 := force_to_dataregister(list, size, reg2);
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if (isaddressregister(reg2)) then
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begin
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hreg2:= getintregister(list,OS_INT);
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2);
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add_move_instruction(instr);
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list.concat(instr);
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end
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else
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hreg2 := reg2;
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if current_settings.cputype in cpu_ColdFire then
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if current_settings.cputype in cpu_coldfire then
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begin
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{ operation only allowed only a longword }
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{!***************************************
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@ -1262,147 +1170,65 @@ unit cgcpu;
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no need to sign extend the value
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!
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}
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if op in [OP_AND,OP_OR,OP_SUB,OP_XOR] then
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sign_extend(list, size, hreg1);
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if op in [OP_AND,OP_OR,OP_XOR] then
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sign_extend(list, size, hreg1);
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sign_extend(list, size, hreg2);
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list.concat(taicpu.op_reg_reg(topcg2tasmop[op],S_L,hreg1, hreg2));
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end
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else
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begin
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list.concat(taicpu.op_reg_reg(topcg2tasmop[op],TCGSize2OpSize[size],hreg1, hreg2));
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end;
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list.concat(taicpu.op_reg_reg(opcode, opsize, hreg1, hreg2));
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{ move back result into destination register }
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if reg2 <> hreg2 then
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begin
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instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2);
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add_move_instruction(instr);
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list.concat(instr);
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end;
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end;
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OP_DIV :
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begin
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internalerror(20020816);
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{ move back result into destination register }
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move_if_needed(list, size, hreg2, reg2);
|
||||
end;
|
||||
OP_DIV,
|
||||
OP_IDIV :
|
||||
begin
|
||||
internalerror(20020816);
|
||||
internalerror(20020816);
|
||||
end;
|
||||
OP_IMUL :
|
||||
OP_MUL,
|
||||
OP_IMUL:
|
||||
begin
|
||||
sign_extend(list, size,reg1);
|
||||
sign_extend(list, size,reg2);
|
||||
if current_settings.cputype<>cpu_MC68020 then
|
||||
call_rtl_mul_reg_reg(list,reg1,reg2,'fpc_mul_longint')
|
||||
if current_settings.cputype <> cpu_mc68020 then
|
||||
if op = OP_MUL then
|
||||
call_rtl_mul_reg_reg(list,reg1,reg2,'fpc_mul_dword')
|
||||
else
|
||||
begin
|
||||
// writeln('doing 68020');
|
||||
call_rtl_mul_reg_reg(list,reg1,reg2,'fpc_mul_longint')
|
||||
else
|
||||
begin
|
||||
{ 68020+ codepath, probably could be improved to
|
||||
include more CPUs... (KB) }
|
||||
hreg1 := force_to_dataregister(list, size, reg1);
|
||||
hreg2 := force_to_dataregister(list, size, reg2);
|
||||
|
||||
if (isaddressregister(reg1)) then
|
||||
hreg1 := getintregister(list,OS_INT)
|
||||
else
|
||||
hreg1 := reg1;
|
||||
if (isaddressregister(reg2)) then
|
||||
hreg2:= getintregister(list,OS_INT)
|
||||
else
|
||||
hreg2 := reg2;
|
||||
sign_extend(list, size, hreg1);
|
||||
sign_extend(list, size, hreg2);
|
||||
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
list.concat(taicpu.op_reg_reg(opcode, opsize, hreg1, hreg2));
|
||||
|
||||
list.concat(taicpu.op_reg_reg(A_MULS,S_L,reg1,reg2));
|
||||
|
||||
{ move back result into destination register }
|
||||
|
||||
if reg2 <> hreg2 then
|
||||
begin
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
OP_MUL :
|
||||
begin
|
||||
sign_extend(list, size,reg1);
|
||||
sign_extend(list, size,reg2);
|
||||
if current_settings.cputype <> cpu_MC68020 then
|
||||
call_rtl_mul_reg_reg(list,reg1,reg2,'fpc_mul_dword')
|
||||
else
|
||||
begin
|
||||
if (isaddressregister(reg1)) then
|
||||
begin
|
||||
hreg1 := cg.getintregister(list,OS_INT);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg1,hreg1);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end
|
||||
else
|
||||
hreg1 := reg1;
|
||||
|
||||
if (isaddressregister(reg2)) then
|
||||
begin
|
||||
hreg2:= cg.getintregister(list,OS_INT);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end
|
||||
else
|
||||
hreg2 := reg2;
|
||||
|
||||
list.concat(taicpu.op_reg_reg(A_MULU,S_L,reg1,reg2));
|
||||
|
||||
{ move back result into destination register }
|
||||
if reg2<>hreg2 then
|
||||
begin
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end;
|
||||
end;
|
||||
{ move back result into destination register }
|
||||
move_if_needed(list, size, hreg2, reg2);
|
||||
end;
|
||||
end;
|
||||
OP_NEG,
|
||||
OP_NOT :
|
||||
Begin
|
||||
begin
|
||||
{ if there are two operands, move the register,
|
||||
since the operation will only be done on the result
|
||||
register.
|
||||
}
|
||||
register. }
|
||||
if reg1 <> NR_NO then
|
||||
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,reg1,reg2);
|
||||
hreg1:=reg1
|
||||
else
|
||||
hreg1:=reg2;
|
||||
|
||||
if (isaddressregister(reg2)) then
|
||||
begin
|
||||
hreg2 := getintregister(list,OS_INT);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg2,hreg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end
|
||||
else
|
||||
hreg2 := reg2;
|
||||
hreg2 := force_to_dataregister(list, size, hreg1);
|
||||
|
||||
{ coldfire only supports long version }
|
||||
if current_settings.cputype in cpu_ColdFire then
|
||||
begin
|
||||
sign_extend(list, size,hreg2);
|
||||
list.concat(taicpu.op_reg(topcg2tasmop[op],S_L,hreg2));
|
||||
end
|
||||
else
|
||||
begin
|
||||
list.concat(taicpu.op_reg(topcg2tasmop[op],TCGSize2OpSize[size],hreg2));
|
||||
end;
|
||||
sign_extend(list, size, hreg2);
|
||||
|
||||
if reg2 <> hreg2 then
|
||||
begin
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,hreg2,reg2);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end;
|
||||
list.concat(taicpu.op_reg(opcode, opsize, hreg2));
|
||||
|
||||
{ move back the result to the result register if needed }
|
||||
move_if_needed(list, size, hreg2, reg2);
|
||||
end;
|
||||
else
|
||||
internalerror(20020729);
|
||||
@ -1414,49 +1240,53 @@ unit cgcpu;
|
||||
procedure tcg68k.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
|
||||
l : tasmlabel);
|
||||
var
|
||||
hregister : tregister;
|
||||
instr : taicpu;
|
||||
hregister : tregister;
|
||||
instr : taicpu;
|
||||
need_temp_reg : boolean;
|
||||
temp_size: topsize;
|
||||
begin
|
||||
if a = 0 then
|
||||
begin
|
||||
if (current_settings.cputype = cpu_MC68000) and isaddressregister(reg) then
|
||||
begin
|
||||
{
|
||||
68000 does not seem to like address register for TST instruction
|
||||
}
|
||||
{ always move to a data register }
|
||||
hregister := getintregister(list,OS_INT);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg,hregister);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
{ sign/zero extend the register }
|
||||
sign_extend(list, size,hregister);
|
||||
reg:=hregister;
|
||||
end;
|
||||
list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg));
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (current_settings.cputype in cpu_ColdFire) then
|
||||
begin
|
||||
{
|
||||
only longword comparison is supported,
|
||||
and only on data registers.
|
||||
}
|
||||
hregister := getintregister(list,OS_INT);
|
||||
{ always move to a data register }
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg,hregister);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
{ sign/zero extend the register }
|
||||
sign_extend(list, size,hregister);
|
||||
list.concat(taicpu.op_const_reg(A_CMPI,S_L,a,hregister));
|
||||
end
|
||||
else
|
||||
begin
|
||||
list.concat(taicpu.op_const_reg(A_CMPI,TCGSize2OpSize[size],a,reg));
|
||||
end;
|
||||
end;
|
||||
need_temp_reg := false;
|
||||
|
||||
{ plain 68000 doesn't support address registers for TST }
|
||||
need_temp_reg := (current_settings.cputype = cpu_mc68000) and
|
||||
(a = 0) and isaddressregister(reg);
|
||||
|
||||
{ ColdFire doesn't support address registers for CMPI }
|
||||
need_temp_reg := need_temp_reg or ((current_settings.cputype in cpu_coldfire)
|
||||
and (a <> 0) and isaddressregister(reg));
|
||||
|
||||
if need_temp_reg then
|
||||
begin
|
||||
hregister := getintregister(list,OS_INT);
|
||||
temp_size := TCGSize2OpSize[size];
|
||||
if temp_size < S_W then
|
||||
temp_size := S_W;
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,temp_size,reg,hregister);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
reg := hregister;
|
||||
|
||||
{ do sign extension if size had to be modified }
|
||||
if temp_size <> TCGSize2OpSize[size] then
|
||||
begin
|
||||
sign_extend(list, size, reg);
|
||||
size:=OS_INT;
|
||||
end;
|
||||
end;
|
||||
|
||||
if a = 0 then
|
||||
list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg))
|
||||
else
|
||||
begin
|
||||
{ ColdFire also needs S_L for CMPI }
|
||||
if current_settings.cputype in cpu_coldfire then
|
||||
begin
|
||||
sign_extend(list, size, reg);
|
||||
size:=OS_INT;
|
||||
end;
|
||||
list.concat(taicpu.op_const_reg(A_CMPI,TCGSize2OpSize[size],a,reg));
|
||||
end;
|
||||
|
||||
{ emit the actual jump to the label }
|
||||
a_jmp_cond(list,cmp_op,l);
|
||||
end;
|
||||
@ -1691,10 +1521,6 @@ unit cgcpu;
|
||||
r,rsp: TRegister;
|
||||
ref : TReference;
|
||||
begin
|
||||
{$ifdef DEBUG_CHARLIE}
|
||||
// writeln('proc entry, localsize:',localsize);
|
||||
{$endif DEBUG_CHARLIE}
|
||||
|
||||
if not nostackframe then
|
||||
begin
|
||||
if localsize<>0 then
|
||||
@ -1756,9 +1582,6 @@ unit cgcpu;
|
||||
if not nostackframe then
|
||||
begin
|
||||
localsize := current_procinfo.calc_stackframe_size;
|
||||
{$ifdef DEBUG_CHARLIE}
|
||||
// writeln('proc exit with stackframe, size:',localsize,' parasize:',parasize);
|
||||
{$endif DEBUG_CHARLIE}
|
||||
list.concat(taicpu.op_reg(A_UNLK,S_NO,NR_FRAME_POINTER_REG));
|
||||
parasize := parasize - target_info.first_parm_offset; { i'm still not 100% confident that this is
|
||||
correct here, but at least it looks less
|
||||
@ -1805,9 +1628,6 @@ unit cgcpu;
|
||||
end
|
||||
else
|
||||
begin
|
||||
{$ifdef DEBUG_CHARLIE}
|
||||
// writeln('proc exit, no stackframe');
|
||||
{$endif DEBUG_CHARLIE}
|
||||
list.concat(taicpu.op_none(A_RTS,S_NO));
|
||||
end;
|
||||
|
||||
@ -1966,6 +1786,41 @@ unit cgcpu;
|
||||
list.concat(ai);
|
||||
end;
|
||||
|
||||
{ ensures a register is a dataregister. this is often used, as 68k can't do lots of
|
||||
operations on an address register. if the register is a dataregister anyway, it
|
||||
just returns it untouched.}
|
||||
function tcg68k.force_to_dataregister(list: TAsmList; size: TCGSize; reg: TRegister): TRegister;
|
||||
var
|
||||
scratch_reg: TRegister;
|
||||
instr: Taicpu;
|
||||
begin
|
||||
if isaddressregister(reg) then
|
||||
begin
|
||||
scratch_reg:=getintregister(list,OS_INT);
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,reg,scratch_reg);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
result:=scratch_reg;
|
||||
end
|
||||
else
|
||||
result:=reg;
|
||||
end;
|
||||
|
||||
{ moves source register to destination register, if the two are not the same. can be used in pair
|
||||
with force_to_dataregister() }
|
||||
procedure tcg68k.move_if_needed(list: TAsmList; size: TCGSize; src: TRegister; dest: TRegister);
|
||||
var
|
||||
instr: Taicpu;
|
||||
begin
|
||||
if (src <> dest) then
|
||||
begin
|
||||
instr:=taicpu.op_reg_reg(A_MOVE,S_L,src,dest);
|
||||
add_move_instruction(instr);
|
||||
list.concat(instr);
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
procedure tcg68k.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user