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Merge of revisions 39731 39825 39849 39912 39913 39914 39924 39935 39999 40000 40001 40026 40115 40132 40163 from trunk to fixes_3_2
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r39731 | pierre | 2018-09-11 08:00:54 +0000 (Tue, 11 Sep 2018) | 1 line
Disable overflow for UDIVX ans SDIVX 64-bit instructions
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--- Merging r39731 into '.':
U compiler/sparcgen/ncpumat.pas
--- Recording mergeinfo for merge of r39731 into '.':
G .
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r39825 | pierre | 2018-09-27 06:59:07 +0000 (Thu, 27 Sep 2018) | 1 line
Add rtl dependency and fix fpcdir value
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--- Merging r39825 into '.':
U packages/ide/compiler/Makefile.fpc
--- Recording mergeinfo for merge of r39825 into '.':
G .
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r39849 | pierre | 2018-10-01 21:50:13 +0000 (Mon, 01 Oct 2018) | 1 line
Use vfpv2 as default fpu for eabihf if cpu is below armv7
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--- Merging r39849 into '.':
U compiler/options.pas
--- Recording mergeinfo for merge of r39849 into '.':
G .
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r39912 | pierre | 2018-10-11 20:38:39 +0000 (Thu, 11 Oct 2018) | 1 line
Fix ppuload for string type for i8086, use getasizeint for all string defs but short string
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--- Recording mergeinfo for merge of r39912 into '.':
G .
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r39913 | pierre | 2018-10-11 21:02:25 +0000 (Thu, 11 Oct 2018) | 1 line
fix position of ppuload_platform for trecorddef
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--- Recording mergeinfo for merge of r39913 into '.':
G .
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r39914 | pierre | 2018-10-12 06:05:50 +0000 (Fri, 12 Oct 2018) | 1 line
Adapt ppudump to fix introduced in revision 39912
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--- Recording mergeinfo for merge of r39914 into '.':
G .
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r39924 | pierre | 2018-10-13 11:35:34 +0000 (Sat, 13 Oct 2018) | 1 line
Downgrade some warnings to notes for EXTDEBUG
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--- Merging r39924 into '.':
U compiler/pass_2.pas
U compiler/tgobj.pas
--- Recording mergeinfo for merge of r39924 into '.':
G .
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r39935 | pierre | 2018-10-14 22:18:50 +0000 (Sun, 14 Oct 2018) | 1 line
Add missing setting of expectloc for multiplications
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--- Merging r39935 into '.':
U compiler/nadd.pas
--- Recording mergeinfo for merge of r39935 into '.':
G .
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r39999 | pierre | 2018-10-20 18:44:05 +0000 (Sat, 20 Oct 2018) | 1 line
Avoid run time error if compiled with -CR option
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--- Merging r39999 into '.':
U compiler/m68k/cpupara.pas
--- Recording mergeinfo for merge of r39999 into '.':
G .
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r40000 | pierre | 2018-10-20 18:49:53 +0000 (Sat, 20 Oct 2018) | 1 line
Avoid range check error when compiled with -CR
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--- Merging r40000 into '.':
U compiler/m68k/cgcpu.pas
--- Recording mergeinfo for merge of r40000 into '.':
G .
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r40001 | pierre | 2018-10-20 22:19:08 +0000 (Sat, 20 Oct 2018) | 1 line
Add explicit typecast to avoid range check error
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--- Recording mergeinfo for merge of r40001 into '.':
G .
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r40026 | pierre | 2018-10-24 21:37:22 +0000 (Wed, 24 Oct 2018) | 1 line
Explicitly disable range checking
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--- Merging r40026 into '.':
U compiler/x86/cgx86.pas
--- Recording mergeinfo for merge of r40026 into '.':
G .
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r40115 | pierre | 2018-10-31 22:53:11 +0000 (Wed, 31 Oct 2018) | 1 line
Avoid range check error in ReadPosInfo
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--- Recording mergeinfo for merge of r40115 into '.':
G .
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r40132 | pierre | 2018-11-01 07:09:47 +0000 (Thu, 01 Nov 2018) | 1 line
Only call moved if len>0, as otherwise astring local variable is nil, which leads to a range check error for astring[1]
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--- Recording mergeinfo for merge of r40132 into '.':
G .
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r40163 | pierre | 2018-11-01 21:58:54 +0000 (Thu, 01 Nov 2018) | 8 lines
More -CriotR fixes:
* entfile.pas: Change PPU header falgs filed from longint to dword.
* ngtcon.pas: Change local variable startoffset type to aword.
* omfbase.pas: Avoid calling move with a nil string s indexed as s[1],
to avoid a range check error.
* owomflib.pas: Disable range check explicitly in hash computation.
* utils/ppuutils/ppudump.pp: Adapt to flags type change in entfile.pas
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--- Recording mergeinfo for merge of r40163 into '.':
G .
git-svn-id: branches/fixes_3_2@40616 -
This commit is contained in:
pierre
parent
20799193a7
commit
1fafc17016
@ -2549,7 +2549,7 @@ unit cgcpu;
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cg.a_load_const_reg(list,OS_S32,longint(highvalue),hreg);
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{ don't use cg.a_op_const_reg() here, because a possible optimized
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ADDQ/SUBQ wouldn't set the eXtend bit }
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list.concat(taicpu.op_const_reg(opcode,S_L,lowvalue,regdst.reglo));
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list.concat(taicpu.op_const_reg(opcode,S_L,longint(lowvalue),regdst.reglo));
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list.concat(taicpu.op_reg_reg(xopcode,S_L,hreg,regdst.reghi));
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end;
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OP_AND,OP_OR,OP_XOR:
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@ -268,7 +268,7 @@ unit cpupara;
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We also have to figure out a better switch for this, because this is
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now compiler and platform specific... (KB) }
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if (tprocdef(p).proccalloption in [pocall_syscall,pocall_cdecl,pocall_cppdecl]) and
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if (tabstractprocdef(p).proccalloption in [pocall_syscall,pocall_cdecl,pocall_cppdecl]) and
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(target_info.system in [system_m68k_palmos,system_m68k_linux]) and
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assigned(result.def) and
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(result.def.typ in [stringdef,pointerdef,classrefdef,objectdef,
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@ -408,9 +408,9 @@ unit cpupara;
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return a struct by address. we will probably need some kind of a
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switch to support these various ABIs when generating cdecl calls (KB) }
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if ((vo_is_funcret in hp.varoptions) and
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(tprocdef(p).proccalloption in [pocall_cdecl,pocall_cppdecl]) and
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(tabstractprocdef(p).proccalloption in [pocall_cdecl,pocall_cppdecl]) and
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(target_info.system in [system_m68k_linux]) and
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(tprocdef(p).returndef.typ = recorddef)) then
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(tabstractprocdef(p).returndef.typ = recorddef)) then
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begin
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paraloc^.loc:=LOC_REGISTER;
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paraloc^.register:=NR_M68K_STRUCT_RESULT_REG;
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@ -3604,6 +3604,7 @@ implementation
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begin
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{ if the code generator can handle 32 to 64-bit muls,
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we're done here }
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expectloc:=LOC_REGISTER;
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end
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{$ifndef cpu64bitalu}
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{ is there a 64 bit type ? }
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@ -4091,7 +4091,10 @@ begin
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{ Set FPU type }
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if not(option.FPUSetExplicitly) then
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begin
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init_settings.fputype:=fpu_vfpv3_d16
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if init_settings.cputype < cpu_armv7 then
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init_settings.fputype:=fpu_vfpv2
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else
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init_settings.fputype:=fpu_vfpv3_d16;
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end
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else
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begin
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@ -210,7 +210,14 @@ implementation
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if (not codegenerror) then
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begin
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if (p.location.loc<>p.expectloc) then
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Comment(V_Warning,'Location ('+tcgloc2str[p.location.loc]+') not equal to expectloc ('+tcgloc2str[p.expectloc]+'): '+nodetype2str[p.nodetype]);
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begin
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if ((p.location.loc=loc_register) and (p.expectloc=loc_cregister))
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or ((p.location.loc=loc_fpuregister) and (p.expectloc=loc_cfpuregister))
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or ((p.location.loc=loc_reference) and (p.expectloc=loc_creference)) then
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Comment(V_Note,'Location ('+tcgloc2str[p.location.loc]+') not equal to expectloc ('+tcgloc2str[p.expectloc]+'): '+nodetype2str[p.nodetype])
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else
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Comment(V_Warning,'Location ('+tcgloc2str[p.location.loc]+') not equal to expectloc ('+tcgloc2str[p.expectloc]+'): '+nodetype2str[p.nodetype]);
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end;
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if (p.location.loc=LOC_INVALID) then
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Comment(V_Warning,'Location not set in secondpass: '+nodetype2str[p.nodetype]);
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end;
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@ -94,6 +94,7 @@ implementation
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resultreg : tregister;
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overflowlabel : tasmlabel;
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ai : taicpu;
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no_overflow : boolean;
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begin
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secondpass(left);
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secondpass(right);
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@ -140,6 +141,14 @@ implementation
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op := divops[true, is_signed(right.resultdef),
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cs_check_overflow in current_settings.localswitches];
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if op=A_NOP then
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{ current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('Wrong code generated here'))); }
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begin
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no_overflow:=true;
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op:=divops[true,is_signed(right.resultdef),false];
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end
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else
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no_overflow:=false;
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if (divider<>NR_NO) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,numerator,divider,resultreg))
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else
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@ -147,12 +156,16 @@ implementation
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if (nodetype = modn) then
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begin
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current_asmdata.getjumplabel(overflowlabel);
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ai:=taicpu.op_cond_sym(A_Bxx,C_VS,overflowlabel);
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ai.delayslot_annulled:=true;
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current_asmdata.CurrAsmList.concat(ai);
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if not no_overflow then
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begin
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current_asmdata.getjumplabel(overflowlabel);
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ai:=taicpu.op_cond_sym(A_Bxx,C_VS,overflowlabel);
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ai.delayslot_annulled:=true;
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current_asmdata.CurrAsmList.concat(ai);
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_NOT,resultreg));
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cg.a_label(current_asmdata.CurrAsmList,overflowlabel);
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if not no_overflow then
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cg.a_label(current_asmdata.CurrAsmList,overflowlabel);
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if (divider<>NR_NO) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULX,resultreg,divider,resultreg))
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else
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@ -4561,7 +4561,6 @@ implementation
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end
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else
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begin
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ppuload_platform(ppufile);
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symtable:=trecordsymtable.create(objrealname^,0,0,0);
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trecordsymtable(symtable).fieldalignment:=shortint(ppufile.getbyte);
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trecordsymtable(symtable).recordalignment:=shortint(ppufile.getbyte);
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@ -4571,6 +4570,9 @@ implementation
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trecordsymtable(symtable).datasize:=ppufile.getasizeint;
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trecordsymtable(symtable).paddingsize:=ppufile.getword;
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ppufile.getsmallset(trecordsymtable(symtable).managementoperators);
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{ position of ppuload_platform call must correspond
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to position of writeentry in ppuwrite method }
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ppuload_platform(ppufile);
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trecordsymtable(symtable).ppuload(ppufile);
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{ the variantrecdesc is needed only for iso-like new statements new(prec,1,2,3 ...);
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but because iso mode supports no units, there is no need to store the variantrecdesc
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@ -488,7 +488,10 @@ implementation
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if not(hp^.temptype in temptypes) then
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begin
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{$ifdef EXTDEBUG}
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Comment(V_Warning,'tgobj: (Freetemp) temp at pos '+tostr(pos.val)+ ' has different type ('+TempTypeStr[hp^.temptype]+'), not releasing');
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if hp^.temptype = tt_persistent then
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Comment(V_Note,'tgobj: (Freetemp) temp at pos '+tostr(pos.val)+ ' has different type ('+TempTypeStr[hp^.temptype]+'), not releasing')
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else
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Comment(V_Warning,'tgobj: (Freetemp) temp at pos '+tostr(pos.val)+ ' has different type ('+TempTypeStr[hp^.temptype]+'), not releasing');
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list.concat(tai_tempalloc.allocinfo(hp^.pos,hp^.size,'temp has wrong type ('+TempTypeStr[hp^.temptype]+') not releasing'));
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{$endif}
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exit;
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@ -376,6 +376,10 @@ unit cgx86;
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end;
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{ Range check must be disabled explicitly as the code serves
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on three different architecture sizes }
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{$R-}
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{****************************************************************************
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This is private property, keep out! :)
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****************************************************************************}
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@ -6,7 +6,7 @@
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main=ide
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[require]
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packages=rtl-extra
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packages=rtl rtl-extra
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[target]
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units=compunit
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@ -20,7 +20,7 @@ includedir=$(COMPILERDIR) $(COMPILERDIR)/$(PPC_TARGET)
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fpcpackage=y
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[default]
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fpcdir=../..
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fpcdir=../../..
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[prerules]
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COMPILERDIR=$(FPCDIR)/compiler
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