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* arm compiler can be compiled; far from being working

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This commit is contained in:
florian 2003-08-21 03:14:00 +00:00
parent 0a4508fffd
commit 20b5945be0
5 changed files with 391 additions and 30 deletions
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53
compiler/arm/cgcpu.pas
View File

@ -84,9 +84,6 @@ unit cgcpu;
procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aword; delsource,loadref : boolean);override;
procedure g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef); override;
{ find out whether a is of the form 11..00..11b or 00..11...00. If }
{ that's the case, we can use rlwinm to do an AND operation }
function get_rlwi_const(a: aword; var l1, l2: longint): boolean;
procedure g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
procedure g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
@ -105,19 +102,6 @@ unit cgcpu;
procedure g_return_from_proc_mac(list : taasmoutput;parasize : aword);
{ Make sure ref is a valid reference for the PowerPC and sets the }
{ base to the value of the index if (base = R_NO). }
{ Returns true if the reference contained a base, index and an }
{ offset or symbol, in which case the base will have been changed }
{ to a tempreg (which has to be freed by the caller) containing }
{ the sum of part of the original reference }
function fixref(list: taasmoutput; var ref: treference): boolean;
{ returns whether a reference can be used immediately in a powerpc }
{ instruction }
function issimpleref(const ref: treference): boolean;
{ contains the common code of a_load_reg_ref and a_load_ref_reg }
procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
ref: treference);
@ -290,7 +274,7 @@ unit cgcpu;
function rotl(d : dword;b : byte) : dword;
begin
result=(d shr (32-b)) or (d shl b);
result:=(d shr (32-b)) or (d shl b);
end;
@ -311,7 +295,7 @@ unit cgcpu;
end;
procedure a_load_const_reg(list : taasmoutput; size: tcgsize; a : aword;reg : tregister);override;
procedure tcgarm.a_load_const_reg(list : taasmoutput; size: tcgsize; a : aword;reg : tregister);
var
imm_shift : byte;
l : tasmlabel;
@ -326,8 +310,8 @@ unit cgcpu;
else
begin
objectlibrary.getdatalabel(l);
aktlocaldata.concat(Tai_const_symbol.Create(l));
aktlocaldata.concat(Tai_const.Create_32bit(a));
current_procinfo.aktlocaldata.concat(Tai_const_symbol.Create(l));
current_procinfo.aktlocaldata.concat(Tai_const.Create_32bit(a));
reference_reset(hr);
hr.symbol:=l;
list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
@ -497,13 +481,36 @@ unit cgcpu;
end;
procedure tcg64farm.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
begin
end;
procedure tcg64farm.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);
begin
end;
procedure tcg64farm.a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : qword;regsrc,regdst : tregister64);
begin
end;
procedure tcg64farm.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);
begin
end;
begin
cg := tcgarm.create;
cg64 :=tcg64farm.create;
cg:=tcgarm.create;
cg64:=tcg64farm.create;
end.
{
$Log$
Revision 1.2 2003-08-20 15:50:12 florian
Revision 1.3 2003-08-21 03:14:00 florian
* arm compiler can be compiled; far from being working
Revision 1.2 2003/08/20 15:50:12 florian
* more arm stuff
Revision 1.1 2003/07/21 16:35:30 florian

9
compiler/arm/cpubase.pas
View File

@ -123,6 +123,7 @@ uses
RS_R9 = $0A; RS_R10 = $0B; RS_R11 = $0C;
RS_R12 = $0D; RS_R13 = $0E; RS_R14 = $0F;
RS_R15 = $10;
RS_PC = RS_R15;
first_supreg = RS_R0;
last_supreg = RS_R15;
@ -365,6 +366,9 @@ uses
{# Constant defining possibly all registers which might require saving }
ALL_REGISTERS = [firstreg..lastreg];
general_registers = [R_R0..R_PC];
general_superregisters = [RS_R0..RS_PC];
{# low and high of the available maximum width integer general purpose }
{ registers }
LoGPReg = R_R0;
@ -631,7 +635,10 @@ implementation
end.
{
$Log$
Revision 1.4 2003-08-20 15:50:13 florian
Revision 1.5 2003-08-21 03:14:00 florian
* arm compiler can be compiled; far from being working
Revision 1.4 2003/08/20 15:50:13 florian
* more arm stuff
Revision 1.3 2003/08/16 13:23:01 florian

14
compiler/arm/cpunode.pas
View File

@ -35,17 +35,19 @@ unit cpunode;
the processor specific nodes must be included
after the generic one (FK)
}
narmadd,
narmcal,
narminl,
narmadd
//!!! narminl,
{ this not really a node }
narmmat,
narmcnv
//!!! narmmat,
//!!! narmcnv
;
end.
{
$Log$
Revision 1.1 2003-07-21 16:35:30 florian
Revision 1.2 2003-08-21 03:14:00 florian
* arm compiler can be compiled; far from being working
Revision 1.1 2003/07/21 16:35:30 florian
* very basic stuff for the arm
}

57
compiler/arm/cputarg.pas Normal file
View File

@ -0,0 +1,57 @@
{
$Id$
Copyright (c) 2001-2002 by Peter Vreman
Includes the arm dependent target units
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit cputarg;
{$i fpcdefs.inc}
interface
implementation
uses
systems { prevent a syntax error when nothing is included }
{**************************************
Targets
**************************************}
{$ifndef NOTARGETLINUX}
,t_linux
{$endif}
{**************************************
Assemblers
**************************************}
{$ifndef NOAGARMGAS}
,agarmgas
{$endif}
;
end.
{
$Log$
Revision 1.1 2003-08-21 03:14:00 florian
* arm compiler can be compiled; far from being working
}

288
compiler/arm/narmadd.pas Normal file
View File

@ -0,0 +1,288 @@
{
$Id$
Copyright (c) 2000-2002 by Florian Klaempfl
Code generation for add nodes on the ARM
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit narmadd;
{$i fpcdefs.inc}
interface
uses
node,ncgadd,cpubase,cginfo;
type
tarmaddnode = class(tcgaddnode)
private
function GetResFlags(unsigned:Boolean):TResFlags;
protected
procedure second_addfloat;override;
procedure second_cmpfloat;override;
procedure second_cmpboolean;override;
procedure second_cmpsmallset;override;
procedure second_cmp64bit;override;
procedure second_cmpordinal;override;
end;
implementation
uses
globtype,systems,
cutils,verbose,globals,
symconst,symdef,paramgr,
aasmbase,aasmtai,aasmcpu,defutil,htypechk,
cgbase,cpuinfo,pass_1,pass_2,regvars,cgcpu,
cpupara,
ncon,nset,nadd,
ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
{*****************************************************************************
TSparcAddNode
*****************************************************************************}
function tarmaddnode.GetResFlags(unsigned:Boolean):TResFlags;
begin
case NodeType of
equaln:
GetResFlags:=F_EQ;
unequaln:
GetResFlags:=F_NE;
else
if not(unsigned) then
begin
if nf_swaped in flags then
case NodeType of
ltn:
GetResFlags:=F_GT;
lten:
GetResFlags:=F_GE;
gtn:
GetResFlags:=F_LT;
gten:
GetResFlags:=F_LE;
end
else
case NodeType of
ltn:
GetResFlags:=F_LT;
lten:
GetResFlags:=F_LE;
gtn:
GetResFlags:=F_GT;
gten:
GetResFlags:=F_GE;
end;
end
else
begin
if nf_swaped in Flags then
case NodeType of
ltn:
GetResFlags:=F_CC;
lten:
GetResFlags:=F_LS;
gtn:
GetResFlags:=F_HI;
gten:
GetResFlags:=F_CS;
end
else
case NodeType of
ltn:
GetResFlags:=F_HI;
lten:
GetResFlags:=F_CS;
gtn:
GetResFlags:=F_CC;
gten:
GetResFlags:=F_LS;
end;
end;
end;
end;
procedure tarmaddnode.second_addfloat;
var
op : TAsmOp;
begin
{ we will see what instruction set we'll use on the arm for FP
pass_left_right;
if (nf_swaped in flags) then
swapleftright;
case nodetype of
addn :
op:=A_FADDs;
muln :
op:=A_FMULs;
subn :
op:=A_FSUBs;
slashn :
op:=A_FDIVs;
else
internalerror(200306014);
end;
{ force fpureg as location, left right doesn't matter
as both will be in a fpureg }
location_force_fpureg(exprasmlist,left.location,true);
location_force_fpureg(exprasmlist,right.location,(left.location.loc<>LOC_CFPUREGISTER));
location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
if left.location.loc<>LOC_CFPUREGISTER then
location.register:=left.location.register
else
location.register:=right.location.register;
exprasmlist.concat(taicpu.op_reg_reg_reg(op,
left.location.register,right.location.register,location.register));
release_reg_left_right;
}
end;
procedure tarmaddnode.second_cmpfloat;
begin
{ we will see what instruction set we'll use on the arm for FP
pass_left_right;
if (nf_swaped in flags) then
swapleftright;
{ force fpureg as location, left right doesn't matter
as both will be in a fpureg }
location_force_fpureg(exprasmlist,left.location,true);
location_force_fpureg(exprasmlist,right.location,true);
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(true);
exprasmlist.concat(taicpu.op_reg_reg(A_FCMPs,
left.location.register,right.location.register));
{ Delay slot (can only contain integer operation) }
exprasmlist.concat(taicpu.op_none(A_NOP));
release_reg_left_right;
}
end;
procedure tarmaddnode.second_cmpboolean;
var
zeroreg : tregister;
begin
{!!!!!!!
pass_left_right;
force_reg_left_right(true,true);
zeroreg.enum:=R_INTREGISTER;
zeroreg.number:=NR_G0;
if right.location.loc = LOC_CONSTANT then
tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
else
exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(true);
release_reg_left_right;
}
end;
procedure tarmaddnode.second_cmpsmallset;
var
zeroreg : tregister;
begin
{!!!!!!!
pass_left_right;
force_reg_left_right(true,true);
zeroreg.enum:=R_INTREGISTER;
zeroreg.number:=NR_G0;
if right.location.loc = LOC_CONSTANT then
tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
else
exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(true);
release_reg_left_right;
}
end;
procedure tarmaddnode.second_cmp64bit;
var
unsigned : boolean;
begin
{!!!!!!!
{$warning TODO 64bit compare}
unsigned:=not(is_signed(left.resulttype.def)) or
not(is_signed(right.resulttype.def));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(unsigned);
release_reg_left_right;
}
end;
procedure tarmaddnode.second_cmpordinal;
var
zeroreg : tregister;
unsigned : boolean;
begin
{!!!!!!!
pass_left_right;
force_reg_left_right(true,true);
unsigned:=not(is_signed(left.resulttype.def)) or
not(is_signed(right.resulttype.def));
zeroreg.enum:=R_INTREGISTER;
zeroreg.number:=NR_G0;
if right.location.loc = LOC_CONSTANT then
tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
else
exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(unsigned);
release_reg_left_right;
}
end;
begin
caddnode:=tarmaddnode;
end.
{
$Log$
Revision 1.1 2003-08-21 03:14:00 florian
* arm compiler can be compiled; far from being working
}