mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2026-01-04 18:26:08 +01:00
* arm compiler can be compiled; far from being working
This commit is contained in:
florian
parent
0a4508fffd
commit
20b5945be0
@ -84,9 +84,6 @@ unit cgcpu;
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procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aword; delsource,loadref : boolean);override;
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procedure g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef); override;
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{ find out whether a is of the form 11..00..11b or 00..11...00. If }
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{ that's the case, we can use rlwinm to do an AND operation }
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function get_rlwi_const(a: aword; var l1, l2: longint): boolean;
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procedure g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
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procedure g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset);override;
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@ -105,19 +102,6 @@ unit cgcpu;
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procedure g_return_from_proc_mac(list : taasmoutput;parasize : aword);
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{ Make sure ref is a valid reference for the PowerPC and sets the }
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{ base to the value of the index if (base = R_NO). }
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{ Returns true if the reference contained a base, index and an }
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{ offset or symbol, in which case the base will have been changed }
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{ to a tempreg (which has to be freed by the caller) containing }
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{ the sum of part of the original reference }
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function fixref(list: taasmoutput; var ref: treference): boolean;
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{ returns whether a reference can be used immediately in a powerpc }
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{ instruction }
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function issimpleref(const ref: treference): boolean;
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{ contains the common code of a_load_reg_ref and a_load_ref_reg }
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procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
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ref: treference);
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@ -290,7 +274,7 @@ unit cgcpu;
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function rotl(d : dword;b : byte) : dword;
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begin
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result=(d shr (32-b)) or (d shl b);
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result:=(d shr (32-b)) or (d shl b);
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end;
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@ -311,7 +295,7 @@ unit cgcpu;
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end;
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procedure a_load_const_reg(list : taasmoutput; size: tcgsize; a : aword;reg : tregister);override;
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procedure tcgarm.a_load_const_reg(list : taasmoutput; size: tcgsize; a : aword;reg : tregister);
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var
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imm_shift : byte;
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l : tasmlabel;
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@ -326,8 +310,8 @@ unit cgcpu;
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else
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begin
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objectlibrary.getdatalabel(l);
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aktlocaldata.concat(Tai_const_symbol.Create(l));
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aktlocaldata.concat(Tai_const.Create_32bit(a));
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current_procinfo.aktlocaldata.concat(Tai_const_symbol.Create(l));
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current_procinfo.aktlocaldata.concat(Tai_const.Create_32bit(a));
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reference_reset(hr);
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hr.symbol:=l;
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list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
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@ -497,13 +481,36 @@ unit cgcpu;
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end;
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procedure tcg64farm.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
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begin
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end;
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procedure tcg64farm.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);
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begin
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end;
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procedure tcg64farm.a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : qword;regsrc,regdst : tregister64);
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begin
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end;
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procedure tcg64farm.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);
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begin
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end;
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begin
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cg := tcgarm.create;
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cg64 :=tcg64farm.create;
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cg:=tcgarm.create;
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cg64:=tcg64farm.create;
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end.
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{
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$Log$
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Revision 1.2 2003-08-20 15:50:12 florian
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Revision 1.3 2003-08-21 03:14:00 florian
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* arm compiler can be compiled; far from being working
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Revision 1.2 2003/08/20 15:50:12 florian
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* more arm stuff
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Revision 1.1 2003/07/21 16:35:30 florian
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@ -123,6 +123,7 @@ uses
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RS_R9 = $0A; RS_R10 = $0B; RS_R11 = $0C;
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RS_R12 = $0D; RS_R13 = $0E; RS_R14 = $0F;
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RS_R15 = $10;
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RS_PC = RS_R15;
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first_supreg = RS_R0;
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last_supreg = RS_R15;
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@ -365,6 +366,9 @@ uses
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{# Constant defining possibly all registers which might require saving }
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ALL_REGISTERS = [firstreg..lastreg];
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general_registers = [R_R0..R_PC];
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general_superregisters = [RS_R0..RS_PC];
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{# low and high of the available maximum width integer general purpose }
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{ registers }
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LoGPReg = R_R0;
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@ -631,7 +635,10 @@ implementation
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end.
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{
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$Log$
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Revision 1.4 2003-08-20 15:50:13 florian
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Revision 1.5 2003-08-21 03:14:00 florian
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* arm compiler can be compiled; far from being working
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Revision 1.4 2003/08/20 15:50:13 florian
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* more arm stuff
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Revision 1.3 2003/08/16 13:23:01 florian
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@ -35,17 +35,19 @@ unit cpunode;
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the processor specific nodes must be included
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after the generic one (FK)
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}
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narmadd,
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narmcal,
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narminl,
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narmadd
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//!!! narminl,
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{ this not really a node }
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narmmat,
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narmcnv
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//!!! narmmat,
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//!!! narmcnv
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;
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end.
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{
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$Log$
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Revision 1.1 2003-07-21 16:35:30 florian
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Revision 1.2 2003-08-21 03:14:00 florian
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* arm compiler can be compiled; far from being working
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Revision 1.1 2003/07/21 16:35:30 florian
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* very basic stuff for the arm
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}
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57
compiler/arm/cputarg.pas
Normal file
57
compiler/arm/cputarg.pas
Normal file
@ -0,0 +1,57 @@
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{
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$Id$
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Copyright (c) 2001-2002 by Peter Vreman
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Includes the arm dependent target units
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cputarg;
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{$i fpcdefs.inc}
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interface
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implementation
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uses
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systems { prevent a syntax error when nothing is included }
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{**************************************
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Targets
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**************************************}
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{$ifndef NOTARGETLINUX}
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,t_linux
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{$endif}
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{**************************************
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Assemblers
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**************************************}
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{$ifndef NOAGARMGAS}
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,agarmgas
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{$endif}
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;
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end.
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{
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$Log$
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Revision 1.1 2003-08-21 03:14:00 florian
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* arm compiler can be compiled; far from being working
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}
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288
compiler/arm/narmadd.pas
Normal file
288
compiler/arm/narmadd.pas
Normal file
@ -0,0 +1,288 @@
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{
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$Id$
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the ARM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase,cginfo;
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type
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tarmaddnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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protected
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpboolean;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_cmpordinal;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,
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aasmbase,aasmtai,aasmcpu,defutil,htypechk,
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cgbase,cpuinfo,pass_1,pass_2,regvars,cgcpu,
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cpupara,
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ncon,nset,nadd,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
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{*****************************************************************************
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TSparcAddNode
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*****************************************************************************}
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function tarmaddnode.GetResFlags(unsigned:Boolean):TResFlags;
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begin
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case NodeType of
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equaln:
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GetResFlags:=F_EQ;
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unequaln:
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GetResFlags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swaped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_GT;
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lten:
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GetResFlags:=F_GE;
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gtn:
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GetResFlags:=F_LT;
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gten:
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GetResFlags:=F_LE;
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LT;
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lten:
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GetResFlags:=F_LE;
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gtn:
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GetResFlags:=F_GT;
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gten:
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GetResFlags:=F_GE;
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end;
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end
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else
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begin
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if nf_swaped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_CC;
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lten:
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GetResFlags:=F_LS;
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gtn:
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GetResFlags:=F_HI;
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gten:
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GetResFlags:=F_CS;
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_HI;
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lten:
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GetResFlags:=F_CS;
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gtn:
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GetResFlags:=F_CC;
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gten:
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GetResFlags:=F_LS;
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end;
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end;
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end;
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end;
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procedure tarmaddnode.second_addfloat;
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var
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op : TAsmOp;
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begin
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{ we will see what instruction set we'll use on the arm for FP
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pass_left_right;
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if (nf_swaped in flags) then
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swapleftright;
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case nodetype of
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addn :
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op:=A_FADDs;
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muln :
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op:=A_FMULs;
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subn :
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op:=A_FSUBs;
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slashn :
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op:=A_FDIVs;
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else
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internalerror(200306014);
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end;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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location_force_fpureg(exprasmlist,left.location,true);
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location_force_fpureg(exprasmlist,right.location,(left.location.loc<>LOC_CFPUREGISTER));
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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if left.location.loc<>LOC_CFPUREGISTER then
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location.register:=left.location.register
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else
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location.register:=right.location.register;
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exprasmlist.concat(taicpu.op_reg_reg_reg(op,
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left.location.register,right.location.register,location.register));
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release_reg_left_right;
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}
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end;
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procedure tarmaddnode.second_cmpfloat;
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begin
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{ we will see what instruction set we'll use on the arm for FP
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pass_left_right;
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if (nf_swaped in flags) then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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location_force_fpureg(exprasmlist,left.location,true);
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location_force_fpureg(exprasmlist,right.location,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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exprasmlist.concat(taicpu.op_reg_reg(A_FCMPs,
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left.location.register,right.location.register));
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{ Delay slot (can only contain integer operation) }
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exprasmlist.concat(taicpu.op_none(A_NOP));
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release_reg_left_right;
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}
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end;
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procedure tarmaddnode.second_cmpboolean;
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var
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zeroreg : tregister;
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begin
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{!!!!!!!
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pass_left_right;
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force_reg_left_right(true,true);
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zeroreg.enum:=R_INTREGISTER;
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zeroreg.number:=NR_G0;
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if right.location.loc = LOC_CONSTANT then
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tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
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else
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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release_reg_left_right;
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}
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end;
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procedure tarmaddnode.second_cmpsmallset;
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var
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zeroreg : tregister;
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begin
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{!!!!!!!
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pass_left_right;
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force_reg_left_right(true,true);
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zeroreg.enum:=R_INTREGISTER;
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zeroreg.number:=NR_G0;
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if right.location.loc = LOC_CONSTANT then
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tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
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else
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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release_reg_left_right;
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}
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end;
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procedure tarmaddnode.second_cmp64bit;
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var
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unsigned : boolean;
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begin
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{!!!!!!!
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{$warning TODO 64bit compare}
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unsigned:=not(is_signed(left.resulttype.def)) or
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not(is_signed(right.resulttype.def));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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release_reg_left_right;
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}
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end;
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procedure tarmaddnode.second_cmpordinal;
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var
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zeroreg : tregister;
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unsigned : boolean;
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begin
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{!!!!!!!
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resulttype.def)) or
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not(is_signed(right.resulttype.def));
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zeroreg.enum:=R_INTREGISTER;
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zeroreg.number:=NR_G0;
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if right.location.loc = LOC_CONSTANT then
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tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,zeroreg)
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else
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,zeroreg));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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release_reg_left_right;
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}
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end;
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begin
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caddnode:=tarmaddnode;
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end.
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{
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$Log$
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Revision 1.1 2003-08-21 03:14:00 florian
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* arm compiler can be compiled; far from being working
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}
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