mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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* converted all the magic nasm codes in the x86 internal asm writer from decimal
to octal in the compiler source, so they match the strings in x86ins.dat git-svn-id: trunk@30566 -
This commit is contained in:
nickysn
parent
68a25e154a
commit
22fb1a3e7e
@ -2207,62 +2207,62 @@ implementation
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c:=ord(codes^);
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inc(codes);
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case c of
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0 :
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&0 :
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break;
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1,2,3 :
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&1,&2,&3 :
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begin
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inc(codes,c);
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inc(len,c);
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end;
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8,9,10 :
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&10,&11,&12 :
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begin
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{$ifdef x86_64}
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rex:=rex or (rexbits(oper[c-8]^.reg) and $F1);
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rex:=rex or (rexbits(oper[c-&10]^.reg) and $F1);
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{$endif x86_64}
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inc(codes);
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inc(len);
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end;
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11 :
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&13 :
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begin
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inc(codes);
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inc(len);
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end;
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4,5,6,7 :
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&4,&5,&6,&7 :
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begin
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if opsize={$ifdef i8086}S_L{$else}S_W{$endif} then
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inc(len,2)
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else
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inc(len);
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end;
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12,13,14,
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16,17,18,
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20,21,22,23,
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40,41,42 :
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&14,&15,&16,
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&20,&21,&22,
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&24,&25,&26,&27,
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&50,&51,&52 :
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inc(len);
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24,25,26,
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31,
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48,49,50 :
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&30,&31,&32,
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&37,
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&60,&61,&62 :
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inc(len,2);
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28,29,30:
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&34,&35,&36:
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begin
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if opsize=S_Q then
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inc(len,8)
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else
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inc(len,4);
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end;
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36,37,38:
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&44,&45,&46:
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inc(len,sizeof(pint));
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44,45,46:
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&54,&55,&56:
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inc(len,8);
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32,33,34,
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52,53,54,
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56,57,58,
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172,173,174 :
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&40,&41,&42,
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&64,&65,&66,
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&70,&71,&72,
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&254,&255,&256 :
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inc(len,4);
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60,61,62,63: ; // ignore vex-coded operand-idx
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208,209,210 :
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&74,&75,&76,&77: ; // ignore vex-coded operand-idx
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&320,&321,&322 :
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begin
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case (oper[c-208]^.ot and OT_SIZE_MASK) of
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case (oper[c-&320]^.ot and OT_SIZE_MASK) of
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{$if defined(i386) or defined(x86_64)}
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OT_BITS16 :
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{$elseif defined(i8086)}
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@ -2277,7 +2277,7 @@ implementation
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{$endif x86_64}
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end;
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end;
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200 :
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&310 :
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{$if defined(x86_64)}
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{ every insentry with code 0310 must be marked with NOX86_64 }
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InternalError(2011051301);
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@ -2286,53 +2286,53 @@ implementation
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{$elseif defined(i8086)}
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{nothing};
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{$endif}
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201 :
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&311 :
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{$if defined(x86_64) or defined(i8086)}
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inc(len)
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{$endif x86_64 or i8086}
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;
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212 :
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&324 :
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{$ifndef i8086}
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inc(len)
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{$endif not i8086}
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;
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214 :
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&326 :
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begin
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{$ifdef x86_64}
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rex:=rex or $48;
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{$endif x86_64}
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end;
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202,
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211,
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213,
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215,
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217,218: ;
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219:
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&312,
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&323,
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&325,
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&327,
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&331,&332: ;
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&333:
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begin
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inc(len);
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exists_prefix_F2 := true;
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end;
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220:
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&334:
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begin
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inc(len);
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exists_prefix_F3 := true;
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end;
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241:
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&361:
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begin
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{$ifndef i8086}
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inc(len);
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exists_prefix_66 := true;
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{$endif not i8086}
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end;
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221:
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&335:
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{$ifdef x86_64}
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omit_rexw:=true
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{$endif x86_64}
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;
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64..151 :
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&100..&227 :
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begin
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{$ifdef x86_64}
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if (c<127) then
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if (c<&177) then
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begin
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if (oper[c and 7]^.typ=top_reg) then
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begin
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@ -2350,8 +2350,8 @@ implementation
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{$endif x86_64}
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end;
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242: // VEX prefix for AVX (length = 2 or 3 bytes, dependens on REX.XBW or opcode-prefix ($0F38 or $0F3A))
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// =>> DEFAULT = 2 Bytes
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&362: // VEX prefix for AVX (length = 2 or 3 bytes, dependens on REX.XBW or opcode-prefix ($0F38 or $0F3A))
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// =>> DEFAULT = 2 Bytes
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begin
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if not(exists_vex) then
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begin
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@ -2359,8 +2359,8 @@ implementation
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exists_vex := true;
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end;
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end;
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243: // REX.W = 1
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// =>> VEX prefix length = 3
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&363: // REX.W = 1
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// =>> VEX prefix length = 3
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begin
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if not(exists_vex_extension) then
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begin
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@ -2368,14 +2368,14 @@ implementation
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exists_vex_extension := true;
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end;
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end;
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244: ; // VEX length bit
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246, // operand 2 (ymmreg) encoded immediate byte (bit 4-7)
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247: inc(len); // operand 3 (ymmreg) encoded immediate byte (bit 4-7)
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248: // VEX-Extension prefix $0F
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// ignore for calculating length
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;
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249, // VEX-Extension prefix $0F38
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250: // VEX-Extension prefix $0F3A
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&364: ; // VEX length bit
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&366, // operand 2 (ymmreg) encoded immediate byte (bit 4-7)
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&367: inc(len); // operand 3 (ymmreg) encoded immediate byte (bit 4-7)
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&370: // VEX-Extension prefix $0F
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// ignore for calculating length
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;
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&371, // VEX-Extension prefix $0F38
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&372: // VEX-Extension prefix $0F3A
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begin
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if not(exists_vex_extension) then
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begin
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@ -2383,7 +2383,7 @@ implementation
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exists_vex_extension := true;
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end;
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end;
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192,193,194:
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&300,&301,&302:
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begin
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{$if defined(x86_64) or defined(i8086)}
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if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
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@ -2645,28 +2645,28 @@ implementation
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inc(codes);
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case c of
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0: break;
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1,
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2,
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3: inc(codes,c);
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60: opmode := 0;
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61: opmode := 1;
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62: opmode := 2;
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219: VEXvvvv := VEXvvvv OR $02; // set SIMD-prefix $F3
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220: VEXvvvv := VEXvvvv OR $03; // set SIMD-prefix $F2
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241: VEXvvvv := VEXvvvv OR $01; // set SIMD-prefix $66
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242: needed_VEX := true;
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243: begin
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&0: break;
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&1,
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&2,
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&3: inc(codes,c);
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&74: opmode := 0;
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&75: opmode := 1;
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&76: opmode := 2;
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&333: VEXvvvv := VEXvvvv OR $02; // set SIMD-prefix $F3
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&334: VEXvvvv := VEXvvvv OR $03; // set SIMD-prefix $F2
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&361: VEXvvvv := VEXvvvv OR $01; // set SIMD-prefix $66
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&362: needed_VEX := true;
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&363: begin
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needed_VEX_Extension := true;
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VEXvvvv := VEXvvvv OR (1 shl 7); // set REX.W
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end;
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244: VEXvvvv := VEXvvvv OR $04; // vectorlength = 256 bits AND no scalar
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248: VEXmmmmm := VEXmmmmm OR $01; // set leading opcode byte $0F
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249: begin
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&364: VEXvvvv := VEXvvvv OR $04; // vectorlength = 256 bits AND no scalar
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&370: VEXmmmmm := VEXmmmmm OR $01; // set leading opcode byte $0F
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&371: begin
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needed_VEX_Extension := true;
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VEXmmmmm := VEXmmmmm OR $02; // set leading opcode byte $0F38
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end;
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250: begin
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&372: begin
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needed_VEX_Extension := true;
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VEXmmmmm := VEXmmmmm OR $03; // set leading opcode byte $0F3A
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end;
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@ -2755,9 +2755,9 @@ implementation
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c:=ord(codes^);
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inc(codes);
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case c of
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0 :
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&0 :
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break;
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1,2,3 :
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&1,&2,&3 :
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begin
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{$ifdef x86_64}
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if not(needed_VEX) then // TG
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@ -2766,7 +2766,7 @@ implementation
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objdata.writebytes(codes^,c);
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inc(codes,c);
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end;
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4,6 :
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&4,&6 :
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begin
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case oper[0]^.reg of
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NR_CS:
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@ -2781,11 +2781,11 @@ implementation
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else
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internalerror(777004);
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end;
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if c=4 then
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if c=&4 then
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inc(bytes[0]);
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objdata.writebytes(bytes,1);
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end;
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5,7 :
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&5,&7 :
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begin
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case oper[0]^.reg of
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NR_FS:
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@ -2795,29 +2795,29 @@ implementation
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else
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internalerror(777005);
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end;
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if c=5 then
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if c=&5 then
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inc(bytes[0]);
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objdata.writebytes(bytes,1);
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end;
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8,9,10 :
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&10,&11,&12 :
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begin
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{$ifdef x86_64}
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if not(needed_VEX) then // TG
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maybewriterex;
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{$endif x86_64}
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bytes[0]:=ord(codes^)+regval(oper[c-8]^.reg);
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bytes[0]:=ord(codes^)+regval(oper[c-&10]^.reg);
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inc(codes);
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objdata.writebytes(bytes,1);
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end;
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11 :
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&13 :
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begin
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bytes[0]:=ord(codes^)+condval[condition];
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inc(codes);
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objdata.writebytes(bytes,1);
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end;
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12,13,14 :
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&14,&15,&16 :
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begin
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getvalsym(c-12);
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getvalsym(c-&14);
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if (currval<-128) or (currval>127) then
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Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
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if assigned(currsym) then
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@ -2825,9 +2825,9 @@ implementation
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else
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objdata.writebytes(currval,1);
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end;
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16,17,18 :
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&20,&21,&22 :
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begin
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getvalsym(c-16);
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getvalsym(c-&20);
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if (currval<-256) or (currval>255) then
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Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
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if assigned(currsym) then
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@ -2835,9 +2835,9 @@ implementation
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else
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objdata.writebytes(currval,1);
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end;
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20,21,22,23 :
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&24,&25,&26,&27 :
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begin
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getvalsym(c-20);
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getvalsym(c-&24);
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if (currval<0) or (currval>255) then
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Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
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if assigned(currsym) then
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@ -2845,9 +2845,9 @@ implementation
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else
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objdata.writebytes(currval,1);
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end;
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24,25,26 : // 030..032
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&30,&31,&32 : // 030..032
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begin
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getvalsym(c-24);
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getvalsym(c-&30);
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{$ifndef i8086}
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{ currval is an aint so this cannot happen on i8086 and causes only a warning }
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if (currval<-65536) or (currval>65535) then
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@ -2858,11 +2858,11 @@ implementation
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else
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objdata.writebytes(currval,2);
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end;
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28,29,30 : // 034..036
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&34,&35,&36 : // 034..036
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{ !!! These are intended (and used in opcode table) to select depending
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on address size, *not* operand size. Works by coincidence only. }
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begin
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getvalsym(c-28);
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getvalsym(c-&34);
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if opsize=S_Q then
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begin
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if assigned(currsym) then
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@ -2878,17 +2878,17 @@ implementation
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objdata.writebytes(currval,4);
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end
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end;
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32,33,34 : // 040..042
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&40,&41,&42 : // 040..042
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begin
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getvalsym(c-32);
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getvalsym(c-&40);
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if assigned(currsym) then
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objdata_writereloc(currval,4,currsym,currabsreloc32)
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else
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objdata.writebytes(currval,4);
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end;
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36,37,38 : // 044..046 - select between word/dword/qword depending on
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&44,&45,&46 :// 044..046 - select between word/dword/qword depending on
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begin // address size (we support only default address sizes).
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getvalsym(c-36);
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getvalsym(c-&44);
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{$if defined(x86_64)}
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if assigned(currsym) then
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objdata_writereloc(currval,8,currsym,currabsreloc)
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@ -2906,9 +2906,9 @@ implementation
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objdata.writebytes(currval,2);
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{$endif}
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end;
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40,41,42 : // 050..052 - byte relative operand
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&50,&51,&52 : // 050..052 - byte relative operand
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begin
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getvalsym(c-40);
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getvalsym(c-&50);
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data:=currval-insend;
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{$push}
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{$r-,q-} { disable also overflow as address returns a qword for x86_64 }
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@ -2919,35 +2919,35 @@ implementation
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Message1(asmw_e_short_jmp_out_of_range,tostr(data));
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objdata.writebytes(data,1);
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end;
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44,45,46: // 054..056 - qword immediate operand
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&54,&55,&56: // 054..056 - qword immediate operand
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begin
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getvalsym(c-44);
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getvalsym(c-&54);
|
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if assigned(currsym) then
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objdata_writereloc(currval,8,currsym,currabsreloc)
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else
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objdata.writebytes(currval,8);
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end;
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52,53,54 : // 064..066 - select between 16/32 address mode, but we support only 32
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&64,&65,&66 : // 064..066 - select between 16/32 address mode, but we support only 32
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begin
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getvalsym(c-52);
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getvalsym(c-&64);
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if assigned(currsym) then
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objdata_writereloc(currval,4,currsym,currrelreloc)
|
||||
else
|
||||
objdata_writereloc(currval-insend,4,nil,currabsreloc32)
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||||
end;
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56,57,58 : // 070..072 - long relative operand
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&70,&71,&72 : // 070..072 - long relative operand
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||||
begin
|
||||
getvalsym(c-56);
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||||
getvalsym(c-&70);
|
||||
if assigned(currsym) then
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||||
objdata_writereloc(currval,4,currsym,currrelreloc)
|
||||
else
|
||||
objdata_writereloc(currval-insend,4,nil,currabsreloc32)
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||||
end;
|
||||
60,61,62 : ; // 074..076 - vex-coded vector operand
|
||||
// ignore
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||||
172,173,174 : // 0254..0256 - dword implicitly sign-extended to 64-bit (x86_64 only)
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||||
&74,&75,&76 : ; // 074..076 - vex-coded vector operand
|
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// ignore
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&254,&255,&256 : // 0254..0256 - dword implicitly sign-extended to 64-bit (x86_64 only)
|
||||
begin
|
||||
getvalsym(c-172);
|
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getvalsym(c-&254);
|
||||
{$ifdef x86_64}
|
||||
{ for i386 as aint type is longint the
|
||||
following test is useless }
|
||||
@ -2960,7 +2960,7 @@ implementation
|
||||
else
|
||||
objdata.writebytes(currval,4);
|
||||
end;
|
||||
192,193,194:
|
||||
&300,&301,&302:
|
||||
begin
|
||||
{$if defined(x86_64) or defined(i8086)}
|
||||
if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
|
||||
@ -2970,7 +2970,7 @@ implementation
|
||||
end;
|
||||
{$endif x86_64 or i8086}
|
||||
end;
|
||||
200 : { fixed 16-bit addr }
|
||||
&310 : { fixed 16-bit addr }
|
||||
{$if defined(x86_64)}
|
||||
{ every insentry having code 0310 must be marked with NOX86_64 }
|
||||
InternalError(2011051302);
|
||||
@ -2982,7 +2982,7 @@ implementation
|
||||
{$elseif defined(i8086)}
|
||||
{nothing};
|
||||
{$endif}
|
||||
201 : { fixed 32-bit addr }
|
||||
&311 : { fixed 32-bit addr }
|
||||
{$if defined(x86_64) or defined(i8086)}
|
||||
begin
|
||||
bytes[0]:=$67;
|
||||
@ -2990,9 +2990,9 @@ implementation
|
||||
end
|
||||
{$endif x86_64 or i8086}
|
||||
;
|
||||
208,209,210 :
|
||||
&320,&321,&322 :
|
||||
begin
|
||||
case oper[c-208]^.ot and OT_SIZE_MASK of
|
||||
case oper[c-&320]^.ot and OT_SIZE_MASK of
|
||||
{$if defined(i386) or defined(x86_64)}
|
||||
OT_BITS16 :
|
||||
{$elseif defined(i8086)}
|
||||
@ -3008,11 +3008,11 @@ implementation
|
||||
{$endif x86_64}
|
||||
end;
|
||||
end;
|
||||
211,
|
||||
213 : {no action needed};
|
||||
&323,
|
||||
&325 : {no action needed};
|
||||
|
||||
212,
|
||||
241:
|
||||
&324,
|
||||
&361:
|
||||
begin
|
||||
{$ifndef i8086}
|
||||
if not(needed_VEX) then
|
||||
@ -3022,13 +3022,13 @@ implementation
|
||||
end;
|
||||
{$endif not i8086}
|
||||
end;
|
||||
214 :
|
||||
&326 :
|
||||
begin
|
||||
{$ifndef x86_64}
|
||||
Message(asmw_e_64bit_not_supported);
|
||||
{$endif x86_64}
|
||||
end;
|
||||
219 :
|
||||
&333 :
|
||||
begin
|
||||
if not(needed_VEX) then
|
||||
begin
|
||||
@ -3036,7 +3036,7 @@ implementation
|
||||
objdata.writebytes(bytes,1);
|
||||
end;
|
||||
end;
|
||||
220 :
|
||||
&334 :
|
||||
begin
|
||||
if not(needed_VEX) then
|
||||
begin
|
||||
@ -3044,17 +3044,17 @@ implementation
|
||||
objdata.writebytes(bytes,1);
|
||||
end;
|
||||
end;
|
||||
221:
|
||||
&335:
|
||||
;
|
||||
202,
|
||||
215,
|
||||
217,218 :
|
||||
&312,
|
||||
&327,
|
||||
&331,&332 :
|
||||
begin
|
||||
{ these are dissambler hints or 32 bit prefixes which
|
||||
are not needed }
|
||||
end;
|
||||
242..244: ; // VEX flags =>> nothing todo
|
||||
246: begin
|
||||
&362..&364: ; // VEX flags =>> nothing todo
|
||||
&366: begin
|
||||
if needed_VEX then
|
||||
begin
|
||||
if ops = 4 then
|
||||
@ -3075,7 +3075,7 @@ implementation
|
||||
end
|
||||
else Internalerror(2014032004);
|
||||
end;
|
||||
247: begin
|
||||
&367: begin
|
||||
if needed_VEX then
|
||||
begin
|
||||
if ops = 4 then
|
||||
@ -3096,9 +3096,9 @@ implementation
|
||||
end
|
||||
else Internalerror(2014032008);
|
||||
end;
|
||||
248..250: ; // VEX flags =>> nothing todo
|
||||
31,
|
||||
48,49,50 :
|
||||
&370..&372: ; // VEX flags =>> nothing todo
|
||||
&37,
|
||||
&60,&61,&62 :
|
||||
begin
|
||||
InternalError(777006);
|
||||
end
|
||||
@ -3110,9 +3110,9 @@ implementation
|
||||
if (rex<>0) and not(rexwritten) then
|
||||
internalerror(200603191);
|
||||
{$endif x86_64}
|
||||
if (c>=64) and (c<=151) then // 0100..0227
|
||||
if (c>=&100) and (c<=&227) then // 0100..0227
|
||||
begin
|
||||
if (c<127) then // 0177
|
||||
if (c<&177) then // 0177
|
||||
begin
|
||||
if (oper[c and 7]^.typ=top_reg) then
|
||||
rfield:=regval(oper[c and 7]^.reg)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user