m68k: added support for FSIN/FCOS. these are software supported on the 68040, so we should have a separate 68040/060 FPU option too, to avoid these in the future.

git-svn-id: trunk@30257 -
This commit is contained in:
Károly Balogh 2015-03-17 22:52:53 +00:00
parent 882d42eb86
commit 258b42de26
4 changed files with 55 additions and 7 deletions

View File

@ -496,7 +496,7 @@ type
// FPU opcodes
A_FSXX, A_FSEQ, A_FSNE, A_FSLT, A_FSLE, A_FSGT, A_FSGE:
result:=operand_write;
A_FABS,A_FSQRT,A_FNEG:
A_FABS,A_FSQRT,A_FNEG,A_FSIN,A_FCOS:
if ops = 1 then
begin
if opnr = 0 then

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@ -68,7 +68,7 @@ unit cpubase;
a_move16,
{ coldfire v4 instructions }
a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,
{ fpu processor instructions - directly supported only. }
{ fpu processor instructions - directly supported }
{ ieee aware and misc. condition codes not supported }
a_fabs,a_fadd,
a_fbeq,a_fbne,a_fbngt,a_fbgt,a_fbge,a_fbnge,
@ -82,6 +82,8 @@ unit cpubase;
a_fsflmul,a_ftst,
a_ftrapeq,a_ftrapne,a_ftrapgt,a_ftrapngt,a_ftrapge,a_ftrapnge,
a_ftraplt,a_ftrapnlt,a_ftraple,a_ftrapgl,a_ftrapngl,a_ftrapgle,a_ftrapngle,
{ fpu instructions - indirectly supported }
a_fsin,a_fcos,
{ protected instructions }
a_cprestore,a_cpsave,
{ fpu unit protected instructions }

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@ -62,7 +62,7 @@ interface
'move16',
{ coldfire v4 instructions }
'mov3q','mvz','mvs','sats','byterev','ff1',
{ fpu processor instructions - directly supported only. }
{ fpu processor instructions - directly supported }
{ ieee aware and misc. condition codes not supported }
'fabs','fadd',
'fbeq','fbne','fbngt','fbgt','fbge','fbnge',
@ -76,6 +76,8 @@ interface
'fsflmul','ftst',
'ftrapeq','ftrapne','ftrapgt','ftrapngt','ftrapge','ftrapnge',
'ftraplt','ftrapnlt','ftraple','ftrapgl','ftrapngl','ftrapgle','ftrapngle',
{ fpu instructions - indirectly supported }
'fsin','fcos',
{ protected instructions }
'cprestore','cpsave',
{ fpu unit protected instructions }

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@ -34,18 +34,18 @@ interface
function first_sqr_real: tnode; override;
function first_sqrt_real: tnode; override;
{function first_arctan_real: tnode; override;
function first_ln_real: tnode; override;
function first_ln_real: tnode; override;}
function first_cos_real: tnode; override;
function first_sin_real: tnode; override;}
function first_sin_real: tnode; override;
procedure second_abs_real; override;
procedure second_sqr_real; override;
procedure second_sqrt_real; override;
{procedure second_arctan_real; override;
procedure second_ln_real; override;
procedure second_ln_real; override;}
procedure second_cos_real; override;
procedure second_sin_real; override;
procedure second_prefetch; override;
{procedure second_prefetch; override;
procedure second_abs_long; override;}
private
procedure second_do_operation(op: TAsmOp);
@ -112,6 +112,38 @@ implementation
end;
end;
function t68kinlinenode.first_sin_real : tnode;
begin
if (cs_fp_emulation in current_settings.moduleswitches) then
result:=inherited first_sin_real
else
begin
case current_settings.fputype of
fpu_68881:
expectloc:=LOC_FPUREGISTER;
else
internalerror(2015022203);
end;
first_sin_real:=nil;
end;
end;
function t68kinlinenode.first_cos_real : tnode;
begin
if (cs_fp_emulation in current_settings.moduleswitches) then
result:=inherited first_cos_real
else
begin
case current_settings.fputype of
fpu_68881:
expectloc:=LOC_FPUREGISTER;
else
internalerror(2015022203);
end;
first_cos_real:=nil;
end;
end;
procedure t68kinlinenode.second_abs_real;
begin
//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('second_abs_real called!')));
@ -147,6 +179,18 @@ implementation
second_do_operation(A_FSQRT);
end;
procedure t68kinlinenode.second_sin_real;
begin
//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('second_sqrt_real called!')));
second_do_operation(A_FSIN);
end;
procedure t68kinlinenode.second_cos_real;
begin
//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('second_sqrt_real called!')));
second_do_operation(A_FCOS);
end;
procedure t68kinlinenode.second_do_operation(op: TAsmOp);
var
href: TReference;