From 2602f379d79310f9ac8b6521bf8573f5eeee0c27 Mon Sep 17 00:00:00 2001 From: nickysn Date: Sat, 18 Jan 2014 00:38:46 +0000 Subject: [PATCH] * fixes in the 16 to 32-bit multiplication in ti8086addnode.second_mul git-svn-id: trunk@26497 - --- compiler/i8086/n8086add.pas | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/compiler/i8086/n8086add.pas b/compiler/i8086/n8086add.pas index 5479cf88dc..126b379334 100644 --- a/compiler/i8086/n8086add.pas +++ b/compiler/i8086/n8086add.pas @@ -596,15 +596,6 @@ interface procedure ti8086addnode.second_mul(unsigned: boolean); - procedure add_mov(instr: Taicpu); - begin - { Notify the register allocator that we have written a move instruction so - it can try to eliminate it. } - if (instr.oper[0]^.reg<>current_procinfo.framepointer) and (instr.oper[0]^.reg<>NR_STACK_POINTER_REG) then - tcgx86(cg).add_move_instruction(instr); - current_asmdata.CurrAsmList.concat(instr); - end; - var reg:Tregister; ref:Treference; use_ref:boolean; @@ -668,8 +659,9 @@ interface {Allocate an imaginary 32-bit register, which consists of a pair of 16-bit registers and store DX:AX into it} location.register := cg.getintregister(current_asmdata.CurrAsmList,OS_32); - add_mov(Taicpu.Op_reg_reg(A_MOV,S_W,NR_AX,location.register)); - add_mov(Taicpu.Op_reg_reg(A_MOV,S_W,NR_DX,GetNextReg(location.register))); + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_DX,GetNextReg(location.register)); + cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_AX); + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_AX,location.register); end else begin