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Fixed _fini and _init references in cprt0.as

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Add RiscV to fcl-res and fpcres.
Check that constant is a valid imm12 when doing overflow checking.

git-svn-id: branches/laksen/riscv_new@39494 -
This commit is contained in:
Jeppe Johansen 2018-07-23 11:40:55 +00:00
parent a8c82856b1
commit 27ab039366
7 changed files with 38 additions and 7 deletions
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8
compiler/riscv64/cgcpu.pas
View File

@ -215,7 +215,13 @@ implementation
jump if t0=t1
}
tmpreg:=getintregister(list,OS_INT);
list.Concat(taicpu.op_reg_reg_const(A_SLTI,tmpreg,dst,a));
if is_imm12(a) then
list.Concat(taicpu.op_reg_reg_const(A_SLTI,tmpreg,dst,a))
else
begin
a_load_const_reg(list,OS_INT,a,tmpreg);
list.Concat(taicpu.op_reg_reg_reg(A_SLT,tmpreg,dst,tmpreg));
end;
ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,tmpreg,NR_X0,l,0);
if a<0 then

6
packages/fcl-res/src/elfconsts.pp
View File

@ -22,7 +22,8 @@ interface
type
TElfMachineType = (emtnone, emtsparc, emti386, emtm68k, emtppc, emtppc64,
emtarm, emtarmeb, emtia64, emtx86_64, emtalpha,
emtmips, emtmipsel, emtppc64le, emtaarch64);
emtmips, emtmipsel, emtppc64le, emtaarch64,
emtriscv32, emtriscv64);
const
ELFMAGIC = chr($7f)+'ELF';
@ -73,6 +74,7 @@ const
EM_X86_64 = 62;
EM_AARCH64 = 183;
EM_ALPHA = $9026; //unofficial, but used by gnu toolchain
EM_RISCV = 243;
//machine-specific flags
EF_IA_64_ABI64 = $10; //wow, this is really a 64-bit object file!
@ -137,6 +139,8 @@ const
R_ALPHA_REFQUAD = 2;
R_IA64_DIR64LSB = $27;
R_MIPS_32 = 2;
R_RISCV_32 = 1;
R_RISCV_64 = 2;
//fpc resource constants

7
packages/fcl-res/src/elfsubwriter.inc
View File

@ -425,7 +425,12 @@ begin
EM_PPC64 : begin RelocType:=R_PPC64_ADDR64; SectionType:=SHT_RELA; end;
EM_ALPHA : begin RelocType:=R_ALPHA_REFQUAD; SectionType:=SHT_RELA; end;
EM_IA_64 : begin RelocType:=R_IA64_DIR64LSB; SectionType:=SHT_RELA; end;
EM_MIPS : begin RelocType:=R_MIPS_32; SectionType:=SHT_RELA; end;
EM_MIPS : begin RelocType:=R_MIPS_32; SectionType:=SHT_RELA; end;
{$IF _TElfSubWriter_=TElf64SubWriter}
EM_RISCV : begin RelocType:=R_RISCV_64; SectionType:=SHT_RELA; end;
{$ELSE}
EM_RISCV : begin RelocType:=R_RISCV_32; SectionType:=SHT_RELA; end;
{$ENDIF}
else
raise EElfResourceWriterUnknownMachineException.Create('');
end;

4
packages/fcl-res/src/elfwriter.pp
View File

@ -557,7 +557,9 @@ begin
emtia64 : begin fMachineTypeInt:=EM_IA_64; fBits:=ELFCLASS64; fOrder:=ELFDATA2LSB; end;
emtx86_64 : begin fMachineTypeInt:=EM_X86_64; fBits:=ELFCLASS64; fOrder:=ELFDATA2LSB; end;
emtmips : begin fMachineTypeInt:=EM_MIPS; fBits:=ELFCLASS32; fOrder:=ELFDATA2MSB; end;
emtmipsel : begin fMachineTypeInt:=EM_MIPS; fBits:=ELFCLASS32; fOrder:=ELFDATA2LSB; end
emtmipsel : begin fMachineTypeInt:=EM_MIPS; fBits:=ELFCLASS32; fOrder:=ELFDATA2LSB; end;
emtriscv32: begin fMachineTypeInt:=EM_RISCV; fBits:=ELFCLASS32; fOrder:=ELFDATA2LSB; end;
emtriscv64: begin fMachineTypeInt:=EM_RISCV; fBits:=ELFCLASS64; fOrder:=ELFDATA2LSB; end
else
raise EElfResourceWriterUnknownMachineException.Create('');
end;

4
rtl/linux/riscv64/cprt0.as
View File

@ -74,7 +74,7 @@ _start:
sd sp,%pcrel_lo(1b)(x8)
/* Fetch address of fini */
1:auipc x8,%pcrel_hi(_fini)
1:auipc x8,%pcrel_hi(__libc_csu_fini)
addi a2,x8,%pcrel_lo(1b)
/* argc already loaded to a2*/
@ -93,7 +93,7 @@ _start:
/* Set up the other arguments in registers */
1:auipc x8,%pcrel_hi(PASCALMAIN)
addi a1, x8, %pcrel_lo(1b)
1:auipc x8,%pcrel_hi(_init)
1:auipc x8,%pcrel_hi(__libc_csu_init)
addi a4, x8, %pcrel_lo(1b)
/* Push fini */

3
utils/fpcres/fpcres.pas
View File

@ -72,6 +72,7 @@ begin
writeln(' --arch, -a <name> Set object file architecture. Supported architectures:');
writeln(' i386, x86_64, arm (coff)');
writeln(' i386, x86_64, powerpc, powerpc64, arm, armeb, m68k,');
writeln(' riscv32, riscv64,');
writeln(' sparc, alpha, ia64, mips, mipsel (elf)');
writeln(' i386, x86_64, powerpc, powerpc64, arm, aarch64 (mach-o)');
writeln(' bigendian, littleendian (external)');
@ -254,6 +255,8 @@ begin
mtmipsel : Result.MachineType:=emtmipsel;
mtppc64le : Result.MachineType:=emtppc64le;
mtaarch64 : Result.MachineType:=emtaarch64;
mtriscv32 : Result.MachineType:=emtriscv32;
mtriscv64 : Result.MachineType:=emtriscv64;
end;
end;

13
utils/fpcres/target.pas
View File

@ -23,6 +23,7 @@ interface
type
TMachineType = (mtnone, mti386,mtx86_64,mtppc,mtppc64,mtarm,mtarmeb,mtm68k,
mtsparc,mtalpha,mtia64,mtmips,mtmipsel,mtaarch64,mtppc64le,
mtriscv32,mtriscv64,
mtBigEndian,mtLittleEndian);
TMachineTypes = set of TMachineType;
@ -35,6 +36,7 @@ type
(subarm: TSubMachineTypeArm);
mtnone, mti386,mtx86_64,mtppc,mtppc64,mtm68k,
mtsparc,mtalpha,mtia64,mtmips,mtmipsel,mtaarch64,mtppc64le,
mtriscv32,mtriscv64,
mtBigEndian,mtLittleEndian:
(subgen: TSubMachineTypeGeneric);
end;
@ -85,6 +87,8 @@ var
(name : 'mipsel'; formats : [ofElf]), //mtmipsel
(name : 'aarch64'; formats : [ofElf, ofMachO]), //mtaarch64
(name : 'powerpc64le'; formats : [ofElf]), //mtppc64le
(name : 'riscv32'; formats : [ofElf]), //mtriscv32
(name : 'riscv64'; formats : [ofElf]), //mtriscv64
(name : 'bigendian'; formats : [ofExt]), //mtBigEndian
(name : 'littleendian'; formats : [ofExt]) //mtLittleEndian
);
@ -102,7 +106,8 @@ var
mtppc64,mtarm,mtarmeb,
mtm68k,mtsparc,mtalpha,
mtia64,mtmips,mtmipsel,
mtppc64le,mtaarch64]),
mtppc64le,mtaarch64,
mtriscv32,mtriscv64]),
(name : 'coff'; ext : '.o'; machines : [mti386,mtx86_64,mtarm,
mtppc,mtppc64]),
(name : 'xcoff'; ext : '.o'; machines : [mtppc{,mtppc64}]),
@ -159,6 +164,12 @@ var
{$elseif defined(CPUAARCH64)}
machine : mtaarch64;
submachine : (subgen: smtgen_all);
{$elseif defined(CPURISCV32)}
machine : mtriscv32;
submachine : (subgen: smtgen_all);
{$elseif defined(CPURISCV64)}
machine : mtriscv64;
submachine : (subgen: smtgen_all);
{$else}
machine : mti386; //default i386
submachine : (subgen: smtgen_all);