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* fix tcgx86.a_op_reg_reg on x86-64 and make use of it

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git-svn-id: trunk@26636 -
This commit is contained in:
florian 2014-01-30 20:24:41 +00:00
parent 7d7bf1d877
commit 28a8dc42c6
2 changed files with 30 additions and 14 deletions
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5
compiler/x86/cgx86.pas
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@ -1881,7 +1881,10 @@ unit cgx86;
procedure tcgx86.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); procedure tcgx86.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
const const
{$if defined(cpu64bitalu) or defined(cpu32bitalu)} {$if defined(cpu64bitalu)}
REGCX=NR_RCX;
REGCX_Size = OS_64;
{$elseif defined(cpu32bitalu)}
REGCX=NR_ECX; REGCX=NR_ECX;
REGCX_Size = OS_32; REGCX_Size = OS_32;
{$elseif defined(cpu16bitalu)} {$elseif defined(cpu16bitalu)}

39
compiler/x86_64/nx64mat.pas
View File

@ -179,18 +179,19 @@ implementation
procedure tx8664shlshrnode.pass_generate_code; procedure tx8664shlshrnode.pass_generate_code;
var var
op : Tasmop; op : topcg;
opsize : tcgsize; opsize : tcgsize;
mask : aint; mask : aint;
hcountreg : TRegister;
begin begin
secondpass(left); secondpass(left);
secondpass(right); secondpass(right);
{ determine operator } { determine operator }
if nodetype=shln then if nodetype=shln then
op:=A_SHL op:=OP_SHL
else else
op:=A_SHR; op:=OP_SHR;
{ special treatment of 32bit values for backwards compatibility } { special treatment of 32bit values for backwards compatibility }
{ mul optimizations require to keep the sign (FK) } { mul optimizations require to keep the sign (FK) }
@ -212,21 +213,33 @@ implementation
end; end;
{ load left operators in a register } { load left operators in a register }
location_copy(location,left.location); if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,cgsize_orddef(opsize),false); { location_force_reg can be also used to change the size of a register }
(left.location.size<>opsize) then
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
location_reset(location,LOC_REGISTER,opsize);
location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
{ shifting by a constant directly coded: } { shifting by a constant directly coded: }
if (right.nodetype=ordconstn) then if (right.nodetype=ordconstn) then
emit_const_reg(op,tcgsize2opsize[opsize],tordconstnode(right).value and mask,location.register) cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,
tordconstnode(right).value.uvalue and 63,left.location.register,location.register)
else else
begin begin
{ load right operators in a RCX } { load right operators in a register - this
cg.getcpuregister(current_asmdata.CurrAsmList,NR_RCX); is done since most target cpu which will use this
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_RCX); node do not support a shift count in a mem. location (cec)
}
{ right operand is in ECX } if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_RCX); { location_force_reg can be also used to change the size of a register }
emit_reg_reg(op,tcgsize2opsize[opsize],NR_CL,location.register); (right.location.size<>opsize) then
begin
hcountreg:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,cgsize_orddef(opsize),right.location,hcountreg);
end
else
hcountreg:=right.location.register;
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opsize,hcountreg,left.location.register,location.register);
end; end;
end; end;