+ RiscV: UMul64x64_128 assembler implementation

+ test

rtl/riscv64/riscv64.inc

@@ -296,3 +296,12 @@ asm
 end;
 
 {$endif CPURV_HAS_ZBB}
+
+
+{$define FPC_SYSTEM_HAS_UMUL64X64_128}
+function UMul64x64_128(a,b: uint64; out rHi: uint64): uint64; assembler; nostackframe;
+asm
+  mulhu a3,a0,a1
+  mul a0,a0,a1
+  sd a3,(a2)
+end;

tests/test/units/system/tumul64x64_128.pp

@@ -0,0 +1,21 @@
+var
+  s1,s2,dl,dh: qword;
+begin
+  s1:=1;
+  s2:=1;
+  dl:=UMul64x64_128(s1,s2,dh);
+  if (dl<>1) or (dh<>0) then
+    halt(1);
+
+  s1:=$4000000000000001;
+  s2:=$4000000000000001;
+  dl:=UMul64x64_128(s1,s2,dh);
+  if (dl<>qword($8000000000000001)) or (dh<>$1000000000000000) then
+    halt(2);
+
+  s1:=qword($ffffffffffffffff);
+  s2:=qword($ffffffffffffffff);
+  dl:=UMul64x64_128(s1,s2,dh);
+  if (dl<>$0000000000000001) or (dh<>qword($FFFFFFFFFFFFFFFE)) then
+    halt(3);
+end.