mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-14 19:39:31 +02:00
+ patch by J. Gareth Moreton: some new x86 assembler optimizations, resolves #38130
git-svn-id: trunk@47824 -
This commit is contained in:
florian
parent
5cffbad92a
commit
2a990b8167
@ -238,6 +238,8 @@ unit aoptcpu;
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if InsContainsSegRef(taicpu(p)) then
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exit;
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case taicpu(p).opcode Of
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A_ADD:
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Result:=OptPass2ADD(p);
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A_Jcc:
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Result:=OptPass2Jcc(p);
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A_Lea:
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@ -334,6 +336,8 @@ unit aoptcpu;
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end;
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A_TEST, A_OR:
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Result:=PostPeepholeOptTestOr(p);
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A_AND:
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Result:=PostPeepholeOptAnd(p);
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A_MOVSX:
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Result:=PostPeepholeOptMOVSX(p);
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else
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@ -146,12 +146,14 @@ unit aoptx86;
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function OptPass2Jcc(var p : tai) : boolean;
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function OptPass2Lea(var p: tai): Boolean;
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function OptPass2SUB(var p: tai): Boolean;
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function OptPass2ADD(var p : tai): Boolean;
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function PostPeepholeOptMov(var p : tai) : Boolean;
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{$ifdef x86_64} { These post-peephole optimisations only affect 64-bit registers. [Kit] }
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function PostPeepholeOptMovzx(var p : tai) : Boolean;
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function PostPeepholeOptXor(var p : tai) : Boolean;
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{$endif}
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function PostPeepholeOptAnd(var p : tai) : boolean;
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function PostPeepholeOptMOVSX(var p : tai) : boolean;
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function PostPeepholeOptCmp(var p : tai) : Boolean;
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function PostPeepholeOptTestOr(var p : tai) : Boolean;
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@ -5706,6 +5708,55 @@ unit aoptx86;
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Result := True;
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Exit;
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end
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else if reg_and_hp1_is_instr and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(
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((taicpu(hp1).opcode = A_SHR) and (taicpu(p).opcode = A_MOVZX)) or
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((taicpu(hp1).opcode = A_SAR) and (taicpu(p).opcode <> A_MOVZX))
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) and
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(taicpu(hp1).oper[0]^.typ = top_const) and
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SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
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{ Minimum shift value allowed is the bit size of the smallest register - 1 }
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(taicpu(hp1).oper[0]^.val <
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{ Multiply by 8 because tcgsize2size returns bytes, not bits }
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8 * (
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tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)]
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)
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) then
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begin
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{ For:
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movsx %reg1,%reg1 movzx %reg1,%reg1 (same register, just different sizes)
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sar ##, %reg1 shr ##, %reg1
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Move the shift to before the movx instruction if the shift value
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is not too large.
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}
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asml.Remove(hp1);
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asml.InsertBefore(hp1, p);
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taicpu(hp1).oper[1]^.reg := taicpu(p).oper[0]^.reg;
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case taicpu(p).opsize of
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s_BW, S_BL{$ifdef x86_64}, S_BQ{$endif}:
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taicpu(hp1).opsize := S_B;
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S_WL{$ifdef x86_64}, S_WQ{$endif}:
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taicpu(hp1).opsize := S_W;
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{$ifdef x86_64}
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S_LQ:
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taicpu(hp1).opsize := S_L;
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{$endif}
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else
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InternalError(2020112401);
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end;
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if (taicpu(hp1).opcode = A_SHR) then
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DebugMsg(SPeepholeOptimization + 'MovzShr2ShrMovz', hp1)
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else
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DebugMsg(SPeepholeOptimization + 'MovsSar2SarMovs', hp1);
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Result := True;
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end
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else if taicpu(p).opcode=A_MOVZX then
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begin
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{ removes superfluous And's after movzx's }
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@ -5952,132 +6003,181 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass1AND(var p : tai) : boolean;
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var
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hp1 : tai;
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hp1, hp2 : tai;
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MaskLength : Cardinal;
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MaskedBits : TCgInt;
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begin
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Result:=false;
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if GetNextInstruction(p, hp1) then
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{ There are no optimisations for reference targets }
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if (taicpu(p).oper[1]^.typ <> top_reg) then
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Exit;
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while GetNextInstruction(p, hp1) and
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(hp1.typ = ait_instruction) do
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begin
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if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_AND,[]) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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{ the second register must contain the first one, so compare their subreg types }
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(getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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(abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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{ change
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and const1, reg
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and const2, reg
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to
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and (const1 and const2), reg
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}
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if (taicpu(p).oper[0]^.typ = top_const) then
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begin
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taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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RemoveCurrentP(p, hp1);
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Result:=true;
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exit;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_MOVZX,[]) and
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MatchOpType(taicpu(hp1),top_reg,top_reg) and
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SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL{$ifdef x86_64},S_BQ,S_WQ{$endif x86_64}]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ,S_BL,S_WL]))
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{$endif x86_64}
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) then
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if (taicpu(hp1).opcode = A_AND) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
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{ the second register must contain the first one, so compare their subreg types }
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(getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
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(abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
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{ change
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and const1, reg
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and const2, reg
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to
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and (const1 and const2), reg
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}
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
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then
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begin
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{ Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
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32-bit register to a 64-bit register, or even a version called MOVZXD, so
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code that tests for the presence of AND 0xffffffff followed by MOVZX is
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wasted, and is indictive of a compiler bug if it were triggered. [Kit]
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NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
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}
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DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
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RemoveInstruction(hp1);
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Exit;
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end;
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taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
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DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
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RemoveCurrentP(p, hp1);
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Result:=true;
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exit;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_SHL,[]) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
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begin
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else if (taicpu(hp1).opcode = A_MOVZX) and
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MatchOpType(taicpu(hp1),top_reg,top_reg) and
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SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL{$ifdef x86_64},S_BQ,S_WQ{$endif x86_64}]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ,S_BL,S_WL]))
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{$endif x86_64}
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) then
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
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then
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begin
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{ Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
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32-bit register to a 64-bit register, or even a version called MOVZXD, so
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code that tests for the presence of AND 0xffffffff followed by MOVZX is
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wasted, and is indictive of a compiler bug if it were triggered. [Kit]
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NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
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}
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DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
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RemoveInstruction(hp1);
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{ See if there are other optimisations possible }
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Continue;
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end;
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end
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else if (taicpu(hp1).opcode = A_SHL) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
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begin
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{$ifopt R+}
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{$define RANGE_WAS_ON}
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{$R-}
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{$endif}
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{ get length of potential and mask }
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MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
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{ get length of potential and mask }
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MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
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{ really a mask? }
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{ really a mask? }
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{$ifdef RANGE_WAS_ON}
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{$R+}
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{$endif}
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if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
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{ unmasked part shifted out? }
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((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
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begin
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DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
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RemoveCurrentP(p, hp1);
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Result:=true;
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exit;
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end;
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end
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else if MatchOpType(taicpu(p),top_const,top_reg) and
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MatchInstruction(hp1,A_MOVSX{$ifdef x86_64},A_MOVSXD{$endif x86_64},[]) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
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(((taicpu(p).opsize=S_W) and
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(taicpu(hp1).opsize=S_BW)) or
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((taicpu(p).opsize=S_L) and
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(taicpu(hp1).opsize in [S_WL,S_BL]))
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{$ifdef x86_64}
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or
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((taicpu(p).opsize=S_Q) and
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(taicpu(hp1).opsize in [S_BQ,S_WQ,S_LQ]))
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{$endif x86_64}
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) then
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begin
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if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7f)=taicpu(p).oper[0]^.val)
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) or
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(((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7fff)=taicpu(p).oper[0]^.val))
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{$ifdef x86_64}
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or
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(((taicpu(hp1).opsize)=S_LQ) and
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((taicpu(p).oper[0]^.val and $7fffffff)=taicpu(p).oper[0]^.val)
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)
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{$endif x86_64}
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then
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begin
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DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
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RemoveInstruction(hp1);
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Exit;
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end;
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if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
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{ unmasked part shifted out? }
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((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
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begin
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DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
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RemoveCurrentP(p, hp1);
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Result:=true;
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exit;
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end;
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end
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else if (taicpu(p).oper[1]^.typ = top_reg) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).is_jmp) and
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else if (taicpu(hp1).opcode = A_SHR) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
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(taicpu(hp1).oper[0]^.val <= 63) then
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begin
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{ Does SHR combined with the AND cover all the bits?
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e.g. for "andb $252,%reg; shrb $2,%reg" - the "and" can be removed }
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MaskedBits := taicpu(p).oper[0]^.val or ((TCgInt(1) shl taicpu(hp1).oper[0]^.val) - 1);
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if ((taicpu(p).opsize = S_B) and ((MaskedBits and $FF) = $FF)) or
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((taicpu(p).opsize = S_W) and ((MaskedBits and $FFFF) = $FFFF)) or
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((taicpu(p).opsize = S_L) and ((MaskedBits and $FFFFFFFF) = $FFFFFFFF)) then
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begin
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DebugMsg(SPeepholeOptimization + 'AndShrToShr done', p);
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RemoveCurrentP(p, hp1);
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Result := True;
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Exit;
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end;
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end
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else if ((taicpu(hp1).opcode = A_MOVSX){$ifdef x86_64} or (taicpu(hp1).opcode = A_MOVSXD){$endif x86_64}) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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begin
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if SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
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(
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(
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(taicpu(hp1).opsize in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7F) = taicpu(p).oper[0]^.val)
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) or (
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(taicpu(hp1).opsize in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
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((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val)
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{$ifdef x86_64}
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) or (
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(taicpu(hp1).opsize = S_LQ) and
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((taicpu(p).oper[0]^.val and $7fffffff) = taicpu(p).oper[0]^.val)
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{$endif x86_64}
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)
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) then
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begin
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if (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg){$ifdef x86_64} or (taicpu(hp1).opsize = S_LQ){$endif x86_64} then
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begin
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DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
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RemoveInstruction(hp1);
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{ See if there are other optimisations possible }
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Continue;
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end;
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{ The super-registers are the same though.
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Note that this change by itself doesn't improve
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code speed, but it opens up other optimisations. }
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{$ifdef x86_64}
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{ Convert 64-bit register to 32-bit }
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case taicpu(hp1).opsize of
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S_BQ:
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begin
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taicpu(hp1).opsize := S_BL;
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taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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end;
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S_WQ:
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begin
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taicpu(hp1).opsize := S_WL;
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taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
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end
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else
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;
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end;
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{$endif x86_64}
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DebugMsg(SPeepholeOptimization + 'AndMovsxToAndMovzx', hp1);
|
||||
taicpu(hp1).opcode := A_MOVZX;
|
||||
{ See if there are other optimisations possible }
|
||||
Continue;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
if (taicpu(hp1).is_jmp) and
|
||||
(taicpu(hp1).opcode<>A_JMP) and
|
||||
not(RegInUsedRegs(taicpu(p).oper[1]^.reg,UsedRegs)) then
|
||||
begin
|
||||
@ -6093,10 +6193,12 @@ unit aoptx86;
|
||||
taicpu(p).opcode := A_TEST;
|
||||
Exit;
|
||||
end;
|
||||
|
||||
Break;
|
||||
end;
|
||||
|
||||
{ Lone AND tests }
|
||||
if MatchOpType(taicpu(p),top_const,top_reg) then
|
||||
if (taicpu(p).oper[0]^.typ = top_const) then
|
||||
begin
|
||||
{
|
||||
- Convert and $0xFF,reg to and reg,reg if reg is 8-bit
|
||||
@ -6116,6 +6218,94 @@ unit aoptx86;
|
||||
end;
|
||||
end;
|
||||
|
||||
{ Backward check to determine necessity of and %reg,%reg }
|
||||
if (taicpu(p).oper[0]^.typ = top_reg) and
|
||||
(taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
|
||||
not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
|
||||
GetLastInstruction(p, hp2) and
|
||||
RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp2) and
|
||||
{ Check size of adjacent instruction to determine if the AND is
|
||||
effectively a null operation }
|
||||
(
|
||||
(taicpu(p).opsize = taicpu(hp2).opsize) or
|
||||
{ Note: Don't include S_Q }
|
||||
((taicpu(p).opsize = S_L) and (taicpu(hp2).opsize in [S_BL, S_WL])) or
|
||||
((taicpu(p).opsize = S_W) and (taicpu(hp2).opsize in [S_BW, S_BL, S_WL, S_L])) or
|
||||
((taicpu(p).opsize = S_B) and (taicpu(hp2).opsize in [S_BW, S_BL, S_WL, S_W, S_L]))
|
||||
) then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'And2Nop', p);
|
||||
{ If GetNextInstruction returned False, hp1 will be nil }
|
||||
RemoveCurrentP(p, hp1);
|
||||
Result := True;
|
||||
Exit;
|
||||
end;
|
||||
|
||||
end;
|
||||
|
||||
|
||||
function TX86AsmOptimizer.OptPass2ADD(var p : tai) : boolean;
|
||||
var
|
||||
hp1: tai;
|
||||
|
||||
{ This entire nested function is used in an if-statement below, but we
|
||||
want to avoid all the used reg transfers and GetNextInstruction calls
|
||||
until we really have to check }
|
||||
function MemRegisterNotUsedLater: Boolean; inline;
|
||||
var
|
||||
hp2: tai;
|
||||
begin
|
||||
TransferUsedRegs(TmpUsedRegs);
|
||||
hp2 := p;
|
||||
repeat
|
||||
UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
|
||||
until not GetNextInstruction(hp2, hp2) or (hp2 = hp1);
|
||||
|
||||
Result := not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs);
|
||||
end;
|
||||
|
||||
begin
|
||||
Result := False;
|
||||
|
||||
{ Change:
|
||||
add %reg2,%reg1
|
||||
mov/s/z #(%reg1),%reg1 (%reg1 superregisters must be the same)
|
||||
|
||||
To:
|
||||
mov/s/z #(%reg1,%reg2),%reg1
|
||||
}
|
||||
|
||||
if (taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif}]) and
|
||||
MatchOpType(taicpu(p), top_reg, top_reg) and
|
||||
GetNextInstruction(p, hp1) and
|
||||
MatchInstruction(hp1, [A_MOV, A_MOVZX, A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif}], []) and
|
||||
MatchOpType(taicpu(hp1), top_ref, top_reg) and
|
||||
(taicpu(hp1).oper[0]^.ref^.scalefactor <= 1) and
|
||||
(
|
||||
(
|
||||
(taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
|
||||
(taicpu(hp1).oper[0]^.ref^.index = NR_NO)
|
||||
) or (
|
||||
(taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
|
||||
(taicpu(hp1).oper[0]^.ref^.base = NR_NO)
|
||||
)
|
||||
) and (
|
||||
Reg1WriteOverwritesReg2Entirely(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) or
|
||||
(
|
||||
{ If the super registers ARE equal, then this MOV/S/Z does a partial write }
|
||||
not SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
|
||||
MemRegisterNotUsedLater
|
||||
)
|
||||
) then
|
||||
begin
|
||||
taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[1]^.reg;
|
||||
taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
|
||||
|
||||
DebugMsg(SPeepholeOptimization + 'AddMov2Mov done', p);
|
||||
RemoveCurrentp(p, hp1);
|
||||
Result := True;
|
||||
Exit;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -6405,6 +6595,41 @@ unit aoptx86;
|
||||
end;
|
||||
|
||||
|
||||
function TX86AsmOptimizer.PostPeepholeOptAnd(var p : tai) : boolean;
|
||||
var
|
||||
hp1: tai;
|
||||
begin
|
||||
{ Detect:
|
||||
andw x, %ax (0 <= x < $8000)
|
||||
...
|
||||
movzwl %ax,%eax
|
||||
|
||||
Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
|
||||
}
|
||||
|
||||
Result := False;
|
||||
if MatchOpType(taicpu(p), top_const, top_reg) and
|
||||
(taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
|
||||
((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val) and
|
||||
GetNextInstructionUsingReg(p, hp1, NR_EAX) and
|
||||
MatchInstruction(hp1, A_MOVZX, [S_WL]) and
|
||||
MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
|
||||
MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
|
||||
begin
|
||||
DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via AndMovz2AndCwtl)', hp1);
|
||||
taicpu(hp1).opcode := A_CWDE;
|
||||
taicpu(hp1).clearop(0);
|
||||
taicpu(hp1).clearop(1);
|
||||
taicpu(hp1).ops := 0;
|
||||
|
||||
{ A change was made, but not with p, so move forward 1 }
|
||||
p := tai(p.Next);
|
||||
Result := True;
|
||||
end;
|
||||
|
||||
end;
|
||||
|
||||
|
||||
function TX86AsmOptimizer.PostPeepholeOptMOVSX(var p : tai) : boolean;
|
||||
begin
|
||||
Result := False;
|
||||
|
||||
@ -173,6 +173,8 @@ uses
|
||||
Result:=OptPass2Lea(p);
|
||||
A_SUB:
|
||||
Result:=OptPass2SUB(p);
|
||||
A_ADD:
|
||||
Result:=OptPass2ADD(p);
|
||||
else
|
||||
;
|
||||
end;
|
||||
@ -192,6 +194,8 @@ uses
|
||||
case taicpu(p).opcode of
|
||||
A_MOV:
|
||||
Result:=PostPeepholeOptMov(p);
|
||||
A_AND:
|
||||
Result:=PostPeepholeOptAnd(p);
|
||||
A_MOVSX:
|
||||
Result:=PostPeepholeOptMOVSX(p);
|
||||
A_MOVZX:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user