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* m68k: partially improved code generation for comparisons.
git-svn-id: trunk@28283 -
This commit is contained in:
sergei
parent
01c8ee158d
commit
2c8264c42b
@ -244,7 +244,6 @@ implementation
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procedure t68kaddnode.second_cmpordinal;
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var
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unsigned : boolean;
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useconst : boolean;
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tmpreg : tregister;
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opsize : topsize;
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cmpsize : tcgsize;
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@ -255,7 +254,7 @@ implementation
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not(is_signed(right.resultdef));
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{ this puts constant operand (if any) to the right }
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pass_left_right;
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{ tentatively assume left size (correct for possible TST/CMPI, will fix later) }
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{ tentatively assume left size (correct for possible TST, will fix later) }
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cmpsize:=def_cgsize(left.resultdef);
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opsize:=tcgsize2opsize[cmpsize];
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@ -283,37 +282,26 @@ implementation
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exit;
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end;
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{ ToDo : set "allowconstants" to True, but this seems to upset Coldfire
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a bit for the CMP instruction => check manual and implement
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exception accordingly below }
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{ load values into registers (except constants) }
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force_reg_left_right(true, false);
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{ Coldfire supports byte/word compares only starting with ISA_B,
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!!see remark about Qemu weirdness in tcg68k.a_cmp_const_reg_label }
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if (opsize<>S_L) and (current_settings.cputype in cpu_coldfire{-[cpu_isa_b,cpu_isa_c]}) then
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begin
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{ 1) Extension is needed for LOC_REFERENCE, but what about LOC_REGISTER ? Perhaps after fixing cg we can assume
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that high bits of registers are correct.
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2) Assuming that extension depends only on source signedness --> destination OS_32 is acceptable. }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(OS_32),false);
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if (right.location.loc<>LOC_CONSTANT) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,cgsize_orddef(OS_32),false);
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opsize:=S_L;
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end
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else
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{ TODO: support LOC_REFERENCE }
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force_reg_left_right(true, true);
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useconst := false;
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if tcgsize2size[right.location.size]=tcgsize2size[left.location.size] then
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cmpsize:=left.location.size
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if (right.location.loc = LOC_CONSTANT) then
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,opsize,
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longint(right.location.value),left.location.register))
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else
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{ ToDo : zero/sign extend??? }
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if tcgsize2size[right.location.size]<tcgsize2size[left.location.size] then
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cmpsize:=left.location.size
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else
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cmpsize:=right.location.size;
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opsize:=tcgsize2opsize[cmpsize];
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if opsize=S_NO then
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internalerror(2013090301);
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{ Attention: The RIGHT(!) operand is substracted from and must be a
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register! }
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{if (right.location.loc = LOC_CONSTANT) then
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if useconst then
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,opsize,
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longint(right.location.value),left.location.register))
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else
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,opsize,
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tmpreg,left.location.register));
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end
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else}
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,opsize,
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right.location.register,left.location.register));
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end;
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@ -326,6 +314,7 @@ implementation
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procedure t68kaddnode.second_cmp64bit;
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var
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unsigned : boolean;
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href: treference;
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procedure firstjmp64bitcmp;
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var
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@ -385,17 +374,83 @@ implementation
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end;
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begin
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{ This puts constant operand (if any) to the right }
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pass_left_right;
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force_reg_left_right(false,false);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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location_reset(location,LOC_JUMP,OS_NO);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reghi,left.location.register64.reghi));
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firstjmp64bitcmp;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reglo,left.location.register64.reglo));
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secondjmp64bitcmp;
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if (right.location.loc=LOC_CONSTANT) and (right.location.value64=0) and
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(nodetype in [equaln,unequaln]) then
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begin
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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href:=left.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,S_L,href));
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firstjmp64bitcmp;
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inc(href.offset,4);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,S_L,href));
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secondjmp64bitcmp;
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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end;
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else
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,S_L,left.location.register64.reglo));
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firstjmp64bitcmp;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,S_L,left.location.register64.reghi));
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secondjmp64bitcmp;
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end;
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exit;
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end;
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{ left and right no register? }
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{ then one must be demanded }
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if not (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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begin
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if not (right.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true)
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else
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end;
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end;
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{ left is now in register }
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case right.location.loc of
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LOC_REGISTER,LOC_CREGISTER:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reghi,left.location.register64.reghi));
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firstjmp64bitcmp;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reglo,left.location.register64.reglo));
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secondjmp64bitcmp;
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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href:=right.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_CMP,S_L,href,left.location.register64.reghi));
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firstjmp64bitcmp;
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inc(href.offset,4);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_CMP,S_L,href,left.location.register64.reglo));
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secondjmp64bitcmp;
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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LOC_CONSTANT:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(hi(right.location.value64)),left.location.register64.reghi));
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firstjmp64bitcmp;
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(lo(right.location.value64)),left.location.register64.reglo));
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secondjmp64bitcmp;
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end;
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else
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InternalError(2014072501);
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end;
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end;
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