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makefiles: Add support for xtensa-embedded target.
git-svn-id: trunk@44332 -
This commit is contained in:
Jeppe Johansen
parent
30a4f667c1
commit
3189e4245d
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -10613,6 +10613,7 @@ rtl/embedded/system.pp svneol=native#text/plain
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rtl/embedded/systhrd.inc svneol=native#text/plain
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rtl/embedded/sysutils.pp svneol=native#text/pascal
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rtl/embedded/tthread.inc svneol=native#text/plain
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rtl/embedded/xtensa/esp8266.pp svneol=native#text/pascal
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rtl/emx/Makefile svneol=native#text/plain
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rtl/emx/Makefile.fpc svneol=native#text/plain
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rtl/emx/dos.pas svneol=native#text/plain
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@ -91,6 +91,9 @@ endif
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ifeq ($(CPU_TARGET),riscv64)
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PPSUF=rv64
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endif
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ifeq ($(CPU_TARGET),xtensa)
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PPSUF=xtensa
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endif
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# cross compilers uses full cpu_target, not just ppc-suffix
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# (except if the target cannot run a native compiler)
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@ -32,7 +32,7 @@ fpcdir=..
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unexport FPC_VERSION FPC_COMPILERINFO
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# Which platforms are ready for inclusion in the cycle
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CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64
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CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa
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# All supported targets used for clean
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ALLTARGETS=$(CYCLETARGETS)
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@ -89,6 +89,9 @@ endif
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ifdef RISCV64
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PPC_TARGET=riscv64
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endif
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ifdef XTENSA
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PPC_TARGET=xtensa
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endif
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# Default is to generate a compiler for the same
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# platform as CPU_TARGET (a native compiler)
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@ -224,6 +227,9 @@ endif
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ifeq ($(CPC_TARGET),riscv64)
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CPUSUF=rv64
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endif
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ifeq ($(CPC_TARGET),xtensa)
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CPUSUF=xtensa
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endif
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# Do not define the default -d$(CPU_TARGET) because that
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# will conflict with our -d$(CPC_TARGET)
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@ -585,8 +591,8 @@ endif
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# cpu targets
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#####################################################################
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PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64
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PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64
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PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa
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PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64 xtensa
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INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
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SYMLINKINSTALL_TARGETS=$(addsuffix _symlink_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
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@ -984,7 +990,7 @@ ifeq ($(OS_SOURCE),win64)
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EXCLUDE_80BIT_TARGETS=1
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endif
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ifneq ($(findstring $(CPU_SOURCE),aarch64 arm avr jvm m68k mips mipsel powerpc powerpc64 sparc sparc64 riscv32 riscv64),)
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ifneq ($(findstring $(CPU_SOURCE),aarch64 arm avr jvm m68k mips mipsel powerpc powerpc64 sparc sparc64 riscv32 riscv64 xtensa),)
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EXCLUDE_80BIT_TARGETS=1
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endif
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@ -180,6 +180,10 @@ program fpc;
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ppcbin:='ppcrv64';
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processorname:='riscv64';
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{$endif riscv64}
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{$ifdef xtensa}
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ppcbin:='ppcxtensa';
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processorname:='xtensa';
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{$endif xtensa}
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versionstr:=''; { Default is just the name }
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if ParamCount = 0 then
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begin
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@ -263,6 +267,8 @@ program fpc;
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cpusuffix:='sparc64'
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else if processorstr='x86_64' then
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cpusuffix:='x64'
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else if processorstr='xtensa' then
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cpusuffix:='xtensa'
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else
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error('Illegal processor type "'+processorstr+'"');
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@ -221,6 +221,15 @@ $(error No CPUs enabled for given SUBARCH, pass either a SUBARCH or set CPU_UNIT
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endif
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endif
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ifeq ($(ARCH),xtensa)
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CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
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CPU_UNITS=esp8266
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CPU_UNITS_DEFINED=1
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ifeq ($(CPU_UNITS_DEFINED),)
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$(error No CPUs enabled for given SUBARCH, pass either a SUBARCH or set CPU_UNITS_DEFINED=1 if you know what you are doing)
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endif
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endif
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# Paths
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OBJPASDIR=$(RTL)/objpas
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GRAPHDIR=$(INC)/graph
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254
rtl/embedded/xtensa/esp8266.pp
Normal file
254
rtl/embedded/xtensa/esp8266.pp
Normal file
@ -0,0 +1,254 @@
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unit esp8266;
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interface
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const
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//unit: Hz
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APB_CLK_FREQ = 80*1000000;
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UART_CLK_FREQ = APB_CLK_FREQ;
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//divided by 256
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TIMER_CLK_FREQ = (APB_CLK_FREQ shr 8);
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//Peripheral device base address
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PERIPHS_DPORT_BASEADDR = $3ff00000;
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PERIPHS_GPIO_BASEADDR = $60000300;
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PERIPHS_TIMER_BASEDDR = $60000600;
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PERIPHS_RTC_BASEADDR = $60000700;
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PERIPHS_IO_MUX = $60000800;
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//Interrupt remap control registers
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EDGE_INT_ENABLE_REG = (PERIPHS_DPORT_BASEADDR+$04);
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// TM1_EDGE_INT_ENABLE() = SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1);
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// TM1_EDGE_INT_DISABLE() = CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1);
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//GPIO reg
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// GPIO_REG_READ(reg) = READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg);
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// GPIO_REG_WRITE(reg, val) = WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val);
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GPIO_OUT_ADDRESS = $00;
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GPIO_OUT_W1TS_ADDRESS = $04;
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GPIO_OUT_W1TC_ADDRESS = $08;
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GPIO_ENABLE_ADDRESS = $0c;
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GPIO_ENABLE_W1TS_ADDRESS = $10;
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GPIO_ENABLE_W1TC_ADDRESS = $14;
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GPIO_OUT_W1TC_DATA_MASK = $0000ffff;
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GPIO_IN_ADDRESS = $18;
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GPIO_STATUS_ADDRESS = $1c;
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GPIO_STATUS_W1TS_ADDRESS = $20;
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GPIO_STATUS_W1TC_ADDRESS = $24;
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GPIO_STATUS_INTERRUPT_MASK = $0000ffff;
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GPIO_RTC_CALIB_SYNC = PERIPHS_GPIO_BASEADDR+$6c;
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//first write to zero, then to one to start
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RTC_CALIB_START = BIT31;
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//max 8ms
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RTC_PERIOD_NUM_MASK = $3ff;
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GPIO_RTC_CALIB_VALUE = PERIPHS_GPIO_BASEADDR+$70;
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//after measure, flag to one, when start from zero to one, turn to zero
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RTC_CALIB_RDY_S = 31;
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RTC_CALIB_VALUE_MASK = $fffff;
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GPIO_PIN0_ADDRESS = $28;
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GPIO_ID_PIN0 = 0;
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// GPIO_ID_PIN(n) = (GPIO_ID_PIN0+(n));
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GPIO_LAST_REGISTER_ID = 15;
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GPIO_ID_NONE = $ffffffff;
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GPIO_PIN_COUNT = 16;
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GPIO_PIN_CONFIG_MSB = 12;
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GPIO_PIN_CONFIG_LSB = 11;
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GPIO_PIN_CONFIG_MASK = $00001800;
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// GPIO_PIN_CONFIG_GET(x) = (((x) and GPIO_PIN_CONFIG_MASK) shr GPIO_PIN_CONFIG_LSB);
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// GPIO_PIN_CONFIG_SET(x) = (((x) shl GPIO_PIN_CONFIG_LSB) and GPIO_PIN_CONFIG_MASK);
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GPIO_WAKEUP_ENABLE = 1;
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GPIO_WAKEUP_DISABLE = (not GPIO_WAKEUP_ENABLE);
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GPIO_PIN_WAKEUP_ENABLE_MSB = 10;
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GPIO_PIN_WAKEUP_ENABLE_LSB = 10;
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GPIO_PIN_WAKEUP_ENABLE_MASK = $00000400;
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// GPIO_PIN_WAKEUP_ENABLE_GET(x) = (((x) and GPIO_PIN_WAKEUP_ENABLE_MASK) shr GPIO_PIN_WAKEUP_ENABLE_LSB);
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// GPIO_PIN_WAKEUP_ENABLE_SET(x) = (((x) shl GPIO_PIN_WAKEUP_ENABLE_LSB) and GPIO_PIN_WAKEUP_ENABLE_MASK);
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GPIO_PIN_INT_TYPE_MASK = $380;
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GPIO_PIN_INT_TYPE_MSB = 9;
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GPIO_PIN_INT_TYPE_LSB = 7;
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// GPIO_PIN_INT_TYPE_GET(x) = (((x) and GPIO_PIN_INT_TYPE_MASK) shr GPIO_PIN_INT_TYPE_LSB);
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// GPIO_PIN_INT_TYPE_SET(x) = (((x) shl GPIO_PIN_INT_TYPE_LSB) and GPIO_PIN_INT_TYPE_MASK);
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GPIO_PAD_DRIVER_ENABLE = 1;
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GPIO_PAD_DRIVER_DISABLE = (not GPIO_PAD_DRIVER_ENABLE);
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GPIO_PIN_PAD_DRIVER_MSB = 2;
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GPIO_PIN_PAD_DRIVER_LSB = 2;
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GPIO_PIN_PAD_DRIVER_MASK = $00000004;
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// GPIO_PIN_PAD_DRIVER_GET(x) = (((x) and GPIO_PIN_PAD_DRIVER_MASK) shr GPIO_PIN_PAD_DRIVER_LSB);
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// GPIO_PIN_PAD_DRIVER_SET(x) = (((x) shl GPIO_PIN_PAD_DRIVER_LSB) and GPIO_PIN_PAD_DRIVER_MASK);
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GPIO_AS_PIN_SOURCE = 0;
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SIGMA_AS_PIN_SOURCE = (not GPIO_AS_PIN_SOURCE);
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GPIO_PIN_SOURCE_MSB = 0;
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GPIO_PIN_SOURCE_LSB = 0;
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GPIO_PIN_SOURCE_MASK = $00000001;
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// GPIO_PIN_SOURCE_GET(x) = (((x) and GPIO_PIN_SOURCE_MASK) shr GPIO_PIN_SOURCE_LSB);
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// GPIO_PIN_SOURCE_SET(x) = (((x) shl GPIO_PIN_SOURCE_LSB) and GPIO_PIN_SOURCE_MASK);
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// TIMER reg
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// RTC_REG_READ(addr) = READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr);
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// RTC_REG_WRITE(addr, val) = WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val);
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// RTC_CLR_REG_MASK(reg, mask) = CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask);
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// Returns the current time according to the timer timer.
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// NOW() = RTC_REG_READ(FRC2_COUNT_ADDRESS);
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//load initial_value to timer1
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FRC1_LOAD_ADDRESS = $00;
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//timer1's counter value(count from initial_value to 0)
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FRC1_COUNT_ADDRESS = $04;
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FRC1_CTRL_ADDRESS = $08;
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//clear timer1's interrupt when write this address
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FRC1_INT_ADDRESS = $0c;
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FRC1_INT_CLR_MASK = $00000001;
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//timer2's counter value(count from initial_value to 0)
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FRC2_COUNT_ADDRESS = $24;
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//RTC reg
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REG_RTC_BASE = PERIPHS_RTC_BASEADDR;
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RTC_STORE0 = (REG_RTC_BASE + $030);
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RTC_STORE1 = (REG_RTC_BASE + $034);
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RTC_STORE2 = (REG_RTC_BASE + $038);
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RTC_STORE3 = (REG_RTC_BASE + $03C);
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RTC_GPIO_OUT = (REG_RTC_BASE + $068);
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RTC_GPIO_ENABLE = (REG_RTC_BASE + $074);
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RTC_GPIO_IN_DATA = (REG_RTC_BASE + $08C);
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RTC_GPIO_CONF = (REG_RTC_BASE + $090);
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PAD_XPD_DCDC_CONF = (REG_RTC_BASE + $0A0);
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//PIN Mux reg
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PERIPHS_IO_MUX_FUNC = $13;
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PERIPHS_IO_MUX_FUNC_S = 4;
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PERIPHS_IO_MUX_PULLUP = BIT7;
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PERIPHS_IO_MUX_PULLUP2 = BIT6;
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PERIPHS_IO_MUX_SLEEP_PULLUP = BIT3;
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PERIPHS_IO_MUX_SLEEP_PULLUP2 = BIT2;
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PERIPHS_IO_MUX_SLEEP_OE = BIT1;
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PERIPHS_IO_MUX_OE = BIT0;
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PERIPHS_IO_MUX_CONF_U = (PERIPHS_IO_MUX + $00);
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SPI0_CLK_EQU_SYS_CLK = BIT8;
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SPI1_CLK_EQU_SYS_CLK = BIT9;
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PERIPHS_IO_MUX_MTDI_U = (PERIPHS_IO_MUX + $04);
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FUNC_GPIO12 = 3;
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PERIPHS_IO_MUX_MTCK_U = (PERIPHS_IO_MUX + $08);
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FUNC_GPIO13 = 3;
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PERIPHS_IO_MUX_MTMS_U = (PERIPHS_IO_MUX + $0C);
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FUNC_GPIO14 = 3;
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PERIPHS_IO_MUX_MTDO_U = (PERIPHS_IO_MUX + $10);
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FUNC_GPIO15 = 3;
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FUNC_U0RTS = 4;
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PERIPHS_IO_MUX_U0RXD_U = (PERIPHS_IO_MUX + $14);
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FUNC_GPIO3 = 3;
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PERIPHS_IO_MUX_U0TXD_U = (PERIPHS_IO_MUX + $18);
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FUNC_U0TXD = 0;
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FUNC_GPIO1 = 3;
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PERIPHS_IO_MUX_SD_CLK_U = (PERIPHS_IO_MUX + $1c);
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FUNC_SDCLK = 0;
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FUNC_SPICLK = 1;
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PERIPHS_IO_MUX_SD_DATA0_U = (PERIPHS_IO_MUX + $20);
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FUNC_SDDATA0 = 0;
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FUNC_SPIQ = 1;
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FUNC_U1TXD = 4;
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PERIPHS_IO_MUX_SD_DATA1_U = (PERIPHS_IO_MUX + $24);
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FUNC_SDDATA1 = 0;
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FUNC_SPID = 1;
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FUNC_U1RXD = 4;
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FUNC_SDDATA1_U1RXD = 7;
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PERIPHS_IO_MUX_SD_DATA2_U = (PERIPHS_IO_MUX + $28);
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FUNC_SDDATA2 = 0;
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FUNC_SPIHD = 1;
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FUNC_GPIO9 = 3;
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PERIPHS_IO_MUX_SD_DATA3_U = (PERIPHS_IO_MUX + $2c);
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FUNC_SDDATA3 = 0;
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FUNC_SPIWP = 1;
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FUNC_GPIO10 = 3;
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PERIPHS_IO_MUX_SD_CMD_U = (PERIPHS_IO_MUX + $30);
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FUNC_SDCMD = 0;
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FUNC_SPICS0 = 1;
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PERIPHS_IO_MUX_GPIO0_U = (PERIPHS_IO_MUX + $34);
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FUNC_GPIO0 = 0;
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PERIPHS_IO_MUX_GPIO2_U = (PERIPHS_IO_MUX + $38);
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FUNC_GPIO2 = 0;
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FUNC_U1TXD_BK = 2;
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FUNC_U0TXD_BK = 4;
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PERIPHS_IO_MUX_GPIO4_U = (PERIPHS_IO_MUX + $3C);
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FUNC_GPIO4 = 0;
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PERIPHS_IO_MUX_GPIO5_U = (PERIPHS_IO_MUX + $40);
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FUNC_GPIO5 = 0;
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// PIN_PULLUP_DIS(PIN_NAME) = CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP);
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// PIN_PULLUP_EN(PIN_NAME) = SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP);
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implementation
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var
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_stack_top: record end; external name '_stack_top';
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_data: record end; external name '_data';
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_edata: record end; external name '_edata';
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_text_start: record end; external name '_text_start';
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_etext: record end; external name '_etext';
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_bss_start: record end; external name '_bss_start';
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_bss_end: record end; external name '_bss_end';
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procedure Pascalmain; external name 'PASCALMAIN';
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procedure HaltProc; assembler; nostackframe; public name'_haltproc';
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asm
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.Lloop:
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b .Lloop
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end;
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procedure Startup;
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var
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psrc,pdst,pend: plongword;
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begin
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// Copy .text
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psrc:=@_etext;
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pdst:=@_data;
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pend:=@_edata;
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while pdst<pend do
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begin
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pdst^:=psrc^;
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inc(pdst);
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inc(psrc);
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end;
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// Clear .bss
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pend:=@_bss_end;
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while pdst<pend do
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begin
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pdst^:=0;
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inc(pdst);
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end;
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PascalMain;
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Haltproc;
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end;
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procedure LowLevelStartup; assembler; nostackframe;
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asm
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l32r a1, .Lstack_ptr
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j Startup
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.Lstack_ptr:
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.long _stack_top
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end;
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end.
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