diff --git a/compiler/i386/i386nop.inc b/compiler/i386/i386nop.inc
index 9e0fad8df4..3bc72c2604 100644
--- a/compiler/i386/i386nop.inc
+++ b/compiler/i386/i386nop.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86ins.dat }
-2117;
+2118;
diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc
index 7f5cd96ab9..6377b30862 100644
--- a/compiler/i386/i386tab.inc
+++ b/compiler/i386/i386tab.inc
@@ -11358,14 +11358,21 @@
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_xmmreg,ot_xmmreg,ot_xmmrm,ot_none);
-    code    : #241#242#248#1#236#61#80;
+    code    : #232#241#242#248#1#236#61#80;
     flags   : [if_avx,if_sandybridge]
   ),
   (
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_ymmreg,ot_ymmreg,ot_ymmrm,ot_none);
-    code    : #241#242#244#248#1#236#61#80;
+    code    : #232#241#242#244#248#1#236#61#80;
+    flags   : [if_avx2]
+  ),
+  (
+    opcode  : A_VPADDSB;
+    ops     : 3;
+    optypes : (ot_zmmreg,ot_zmmreg,ot_zmmrm,ot_none);
+    code    : #232#233#241#248#1#236#61#80;
     flags   : [if_avx2]
   ),
   (
diff --git a/compiler/i386/r386ari.inc b/compiler/i386/r386ari.inc
index 72d54535fa..7bf45bcf42 100644
--- a/compiler/i386/r386ari.inc
+++ b/compiler/i386/r386ari.inc
@@ -88,4 +88,12 @@
 88,
 89,
 36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97,
 0
diff --git a/compiler/i386/r386att.inc b/compiler/i386/r386att.inc
index bceb36301f..fbb1dfaab9 100644
--- a/compiler/i386/r386att.inc
+++ b/compiler/i386/r386att.inc
@@ -88,4 +88,12 @@
 '%ymm4',
 '%ymm5',
 '%ymm6',
-'%ymm7'
+'%ymm7',
+'%zmm0',
+'%zmm1',
+'%zmm2',
+'%zmm3',
+'%zmm4',
+'%zmm5',
+'%zmm6',
+'%zmm7'
diff --git a/compiler/i386/r386con.inc b/compiler/i386/r386con.inc
index e20b199a27..5c605463a2 100644
--- a/compiler/i386/r386con.inc
+++ b/compiler/i386/r386con.inc
@@ -89,3 +89,11 @@ NR_YMM4 = tregister($040D0004);
 NR_YMM5 = tregister($040D0005);
 NR_YMM6 = tregister($040D0006);
 NR_YMM7 = tregister($040D0007);
+NR_ZMM0 = tregister($040E0000);
+NR_ZMM1 = tregister($040E0001);
+NR_ZMM2 = tregister($040E0002);
+NR_ZMM3 = tregister($040E0003);
+NR_ZMM4 = tregister($040E0004);
+NR_ZMM5 = tregister($040E0005);
+NR_ZMM6 = tregister($040E0006);
+NR_ZMM7 = tregister($040E0007);
diff --git a/compiler/i386/r386dwrf.inc b/compiler/i386/r386dwrf.inc
index 1eb67c19fe..176f7d41e5 100644
--- a/compiler/i386/r386dwrf.inc
+++ b/compiler/i386/r386dwrf.inc
@@ -88,4 +88,12 @@
 25,
 26,
 27,
+28,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
 28
diff --git a/compiler/i386/r386int.inc b/compiler/i386/r386int.inc
index 384ae00310..34afdada88 100644
--- a/compiler/i386/r386int.inc
+++ b/compiler/i386/r386int.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/i386/r386iri.inc b/compiler/i386/r386iri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i386/r386iri.inc
+++ b/compiler/i386/r386iri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i386/r386nasm.inc b/compiler/i386/r386nasm.inc
index 3e96da53e6..aed34e6fa8 100644
--- a/compiler/i386/r386nasm.inc
+++ b/compiler/i386/r386nasm.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/i386/r386nor.inc b/compiler/i386/r386nor.inc
index aa0fcb051c..3e6f7049b4 100644
--- a/compiler/i386/r386nor.inc
+++ b/compiler/i386/r386nor.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86reg.dat }
-90
+98
diff --git a/compiler/i386/r386nri.inc b/compiler/i386/r386nri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i386/r386nri.inc
+++ b/compiler/i386/r386nri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i386/r386num.inc b/compiler/i386/r386num.inc
index 2f0ce1bcb9..5d0be5ed6f 100644
--- a/compiler/i386/r386num.inc
+++ b/compiler/i386/r386num.inc
@@ -88,4 +88,12 @@ tregister($040D0003),
 tregister($040D0004),
 tregister($040D0005),
 tregister($040D0006),
-tregister($040D0007)
+tregister($040D0007),
+tregister($040E0000),
+tregister($040E0001),
+tregister($040E0002),
+tregister($040E0003),
+tregister($040E0004),
+tregister($040E0005),
+tregister($040E0006),
+tregister($040E0007)
diff --git a/compiler/i386/r386ot.inc b/compiler/i386/r386ot.inc
index 95ffb8b8b9..7ee56aee84 100644
--- a/compiler/i386/r386ot.inc
+++ b/compiler/i386/r386ot.inc
@@ -88,4 +88,12 @@ OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
-OT_YMMREG
+OT_YMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG
diff --git a/compiler/i386/r386rni.inc b/compiler/i386/r386rni.inc
index b800d564e9..8de8cfb2a1 100644
--- a/compiler/i386/r386rni.inc
+++ b/compiler/i386/r386rni.inc
@@ -57,6 +57,14 @@
 87,
 88,
 89,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97,
 25,
 26,
 27,
diff --git a/compiler/i386/r386sri.inc b/compiler/i386/r386sri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i386/r386sri.inc
+++ b/compiler/i386/r386sri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i386/r386stab.inc b/compiler/i386/r386stab.inc
index e876c29894..698d4e9bdc 100644
--- a/compiler/i386/r386stab.inc
+++ b/compiler/i386/r386stab.inc
@@ -88,4 +88,12 @@
 25,
 26,
 27,
+28,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
 28
diff --git a/compiler/i386/r386std.inc b/compiler/i386/r386std.inc
index 384ae00310..34afdada88 100644
--- a/compiler/i386/r386std.inc
+++ b/compiler/i386/r386std.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/i8086/i8086nop.inc b/compiler/i8086/i8086nop.inc
index 3edc5df1f5..2094aa4a56 100644
--- a/compiler/i8086/i8086nop.inc
+++ b/compiler/i8086/i8086nop.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86ins.dat }
-2149;
+2150;
diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc
index 0e86e7469d..a70e61fb16 100644
--- a/compiler/i8086/i8086tab.inc
+++ b/compiler/i8086/i8086tab.inc
@@ -11386,14 +11386,21 @@
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_xmmreg,ot_xmmreg,ot_xmmrm,ot_none);
-    code    : #241#242#248#1#236#61#80;
+    code    : #232#241#242#248#1#236#61#80;
     flags   : [if_avx,if_sandybridge]
   ),
   (
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_ymmreg,ot_ymmreg,ot_ymmrm,ot_none);
-    code    : #241#242#244#248#1#236#61#80;
+    code    : #232#241#242#244#248#1#236#61#80;
+    flags   : [if_avx2]
+  ),
+  (
+    opcode  : A_VPADDSB;
+    ops     : 3;
+    optypes : (ot_zmmreg,ot_zmmreg,ot_zmmrm,ot_none);
+    code    : #232#233#241#248#1#236#61#80;
     flags   : [if_avx2]
   ),
   (
diff --git a/compiler/i8086/r8086ari.inc b/compiler/i8086/r8086ari.inc
index 72d54535fa..7bf45bcf42 100644
--- a/compiler/i8086/r8086ari.inc
+++ b/compiler/i8086/r8086ari.inc
@@ -88,4 +88,12 @@
 88,
 89,
 36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97,
 0
diff --git a/compiler/i8086/r8086att.inc b/compiler/i8086/r8086att.inc
index bceb36301f..fbb1dfaab9 100644
--- a/compiler/i8086/r8086att.inc
+++ b/compiler/i8086/r8086att.inc
@@ -88,4 +88,12 @@
 '%ymm4',
 '%ymm5',
 '%ymm6',
-'%ymm7'
+'%ymm7',
+'%zmm0',
+'%zmm1',
+'%zmm2',
+'%zmm3',
+'%zmm4',
+'%zmm5',
+'%zmm6',
+'%zmm7'
diff --git a/compiler/i8086/r8086con.inc b/compiler/i8086/r8086con.inc
index e20b199a27..5c605463a2 100644
--- a/compiler/i8086/r8086con.inc
+++ b/compiler/i8086/r8086con.inc
@@ -89,3 +89,11 @@ NR_YMM4 = tregister($040D0004);
 NR_YMM5 = tregister($040D0005);
 NR_YMM6 = tregister($040D0006);
 NR_YMM7 = tregister($040D0007);
+NR_ZMM0 = tregister($040E0000);
+NR_ZMM1 = tregister($040E0001);
+NR_ZMM2 = tregister($040E0002);
+NR_ZMM3 = tregister($040E0003);
+NR_ZMM4 = tregister($040E0004);
+NR_ZMM5 = tregister($040E0005);
+NR_ZMM6 = tregister($040E0006);
+NR_ZMM7 = tregister($040E0007);
diff --git a/compiler/i8086/r8086dwrf.inc b/compiler/i8086/r8086dwrf.inc
index 1eb67c19fe..176f7d41e5 100644
--- a/compiler/i8086/r8086dwrf.inc
+++ b/compiler/i8086/r8086dwrf.inc
@@ -88,4 +88,12 @@
 25,
 26,
 27,
+28,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
 28
diff --git a/compiler/i8086/r8086int.inc b/compiler/i8086/r8086int.inc
index 384ae00310..34afdada88 100644
--- a/compiler/i8086/r8086int.inc
+++ b/compiler/i8086/r8086int.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/i8086/r8086iri.inc b/compiler/i8086/r8086iri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i8086/r8086iri.inc
+++ b/compiler/i8086/r8086iri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i8086/r8086nasm.inc b/compiler/i8086/r8086nasm.inc
index 3e96da53e6..aed34e6fa8 100644
--- a/compiler/i8086/r8086nasm.inc
+++ b/compiler/i8086/r8086nasm.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/i8086/r8086nor.inc b/compiler/i8086/r8086nor.inc
index aa0fcb051c..3e6f7049b4 100644
--- a/compiler/i8086/r8086nor.inc
+++ b/compiler/i8086/r8086nor.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86reg.dat }
-90
+98
diff --git a/compiler/i8086/r8086nri.inc b/compiler/i8086/r8086nri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i8086/r8086nri.inc
+++ b/compiler/i8086/r8086nri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i8086/r8086num.inc b/compiler/i8086/r8086num.inc
index 2f0ce1bcb9..5d0be5ed6f 100644
--- a/compiler/i8086/r8086num.inc
+++ b/compiler/i8086/r8086num.inc
@@ -88,4 +88,12 @@ tregister($040D0003),
 tregister($040D0004),
 tregister($040D0005),
 tregister($040D0006),
-tregister($040D0007)
+tregister($040D0007),
+tregister($040E0000),
+tregister($040E0001),
+tregister($040E0002),
+tregister($040E0003),
+tregister($040E0004),
+tregister($040E0005),
+tregister($040E0006),
+tregister($040E0007)
diff --git a/compiler/i8086/r8086ot.inc b/compiler/i8086/r8086ot.inc
index 95ffb8b8b9..7ee56aee84 100644
--- a/compiler/i8086/r8086ot.inc
+++ b/compiler/i8086/r8086ot.inc
@@ -88,4 +88,12 @@ OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
-OT_YMMREG
+OT_YMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG
diff --git a/compiler/i8086/r8086rni.inc b/compiler/i8086/r8086rni.inc
index b800d564e9..8de8cfb2a1 100644
--- a/compiler/i8086/r8086rni.inc
+++ b/compiler/i8086/r8086rni.inc
@@ -57,6 +57,14 @@
 87,
 88,
 89,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97,
 25,
 26,
 27,
diff --git a/compiler/i8086/r8086sri.inc b/compiler/i8086/r8086sri.inc
index 2390d1bb14..4d655fd9c1 100644
--- a/compiler/i8086/r8086sri.inc
+++ b/compiler/i8086/r8086sri.inc
@@ -88,4 +88,12 @@
 87,
 88,
 89,
-36
+36,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97
diff --git a/compiler/i8086/r8086stab.inc b/compiler/i8086/r8086stab.inc
index e876c29894..698d4e9bdc 100644
--- a/compiler/i8086/r8086stab.inc
+++ b/compiler/i8086/r8086stab.inc
@@ -88,4 +88,12 @@
 25,
 26,
 27,
+28,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
 28
diff --git a/compiler/i8086/r8086std.inc b/compiler/i8086/r8086std.inc
index 384ae00310..34afdada88 100644
--- a/compiler/i8086/r8086std.inc
+++ b/compiler/i8086/r8086std.inc
@@ -88,4 +88,12 @@
 'ymm4',
 'ymm5',
 'ymm6',
-'ymm7'
+'ymm7',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7'
diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi
index a28f04cf21..a2e62b226b 100644
--- a/compiler/ppcx64.lpi
+++ b/compiler/ppcx64.lpi
@@ -1,4 +1,4 @@
-<?xml version="1.0"?>
+<?xml version="1.0" encoding="UTF-8"?>
 <CONFIG>
   <ProjectOptions>
     <Version Value="9"/>
@@ -19,14 +19,14 @@
     </BuildModes>
     <PublishOptions>
       <Version Value="2"/>
-      <DestinationDirectory Value="$(TestDir)\publishedproject\"/>
       <IncludeFileFilter Value="*.(pas|pp|inc|lfm|lpr|lrs|lpi|lpk|sh|xml)"/>
       <ExcludeFileFilter Value="*.(bak|ppu|ppw|o|so);*~;backup"/>
     </PublishOptions>
     <RunParams>
       <local>
         <FormatVersion Value="1"/>
-        <LaunchingApplication PathPlusParams="/usr/X11R6/bin/xterm -T 'Lazarus Run Output' -e $(LazarusDir)/tools/runwait.sh $(TargetCmdLine)"/>
+        <CommandLineParams Value="\home\torsten\tmp\test.pp"/>
+        <LaunchingApplication PathPlusParams="\usr\X11R6\bin\xterm -T 'Lazarus Run Output' -e $(LazarusDir)\tools\runwait.sh $(TargetCmdLine)"/>
       </local>
     </RunParams>
     <Units Count="2">
diff --git a/compiler/utils/mkx86ins.pp b/compiler/utils/mkx86ins.pp
index a1db21392c..13bea6d97e 100644
--- a/compiler/utils/mkx86ins.pp
+++ b/compiler/utils/mkx86ins.pp
@@ -57,7 +57,7 @@ var
 
 function formatop(s:string;allowsizeonly:boolean):string;
    const
-     replaces=28;
+     replaces=29;
      replacetab : array[1..replaces,1..2] of string[32]=(
        (':',' or ot_colon'),
        ('reg','regnorm'),
@@ -73,6 +73,7 @@ function formatop(s:string;allowsizeonly:boolean):string;
        ('mem64','memory or ot_bits64'),
        ('mem128','memory or ot_bits128'),
        ('mem256','memory or ot_bits256'),
+       ('mem512','memory or ot_bits512'),
        ('mem80','memory or ot_bits80'),
        ('mem','memory'),
        ('memory_offs','mem_offs'),
@@ -282,6 +283,7 @@ begin
      begin
         { handle comment }
         readln(infile,s);
+
         while (s[1]=' ') do
          delete(s,1,1);
         if (s='') or (s[1]=';') then
diff --git a/compiler/utils/mkx86reg.pp b/compiler/utils/mkx86reg.pp
index 29fa8ff2f4..7a3a2c67bc 100644
--- a/compiler/utils/mkx86reg.pp
+++ b/compiler/utils/mkx86reg.pp
@@ -17,7 +17,7 @@
 program mkx86reg;
 
 const Version = '1.00';
-      max_regcount = 200;
+      max_regcount = 255;
 
 var s : string;
     i : longint;
@@ -246,7 +246,7 @@ var infile:text;
 
 begin
    { open dat file }
-   assign(infile,'x86reg.dat');
+   assign(infile,'../x86/x86reg.dat');
    reset(infile);
    while not(eof(infile)) do
      begin
diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas
index ed81af1818..c8da26aa9e 100644
--- a/compiler/x86/aasmcpu.pas
+++ b/compiler/x86/aasmcpu.pas
@@ -50,9 +50,13 @@ interface
       OT_BITS16    = $00000002;
       OT_BITS32    = $00000004;
       OT_BITS64    = $00000008;  { x86_64 and FPU }
-      OT_BITS128   = $10000000;  { 16 byte SSE }
-      OT_BITS256   = $20000000;  { 32 byte AVX }
-      OT_BITS512   = $40000000;  { 64 byte AVX512 }
+      //OT_BITS128   = $10000000;  { 16 byte SSE }
+      //OT_BITS256   = $20000000;  { 32 byte AVX }
+      //OT_BITS512   = $40000000;  { 64 byte AVX512 }
+      OT_BITS128   = $20000000;  { 16 byte SSE }
+      OT_BITS256   = $40000000;  { 32 byte AVX }
+      OT_BITS512   = $80000000;  { 64 byte AVX512 }
+
       OT_BITS80    = $00000010;  { FPU only  }
       OT_FAR       = $00000020;  { this means 16:16 or 16:32, like in CALL/JMP }
       OT_NEAR      = $00000040;
@@ -60,7 +64,8 @@ interface
 
       { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask,
         but this requires adjusting the opcode table }
-      OT_SIZE_MASK = $3000001F;  { all the size attributes  }
+      //OT_SIZE_MASK = $3000001F;  { all the size attributes  }
+      OT_SIZE_MASK = $E000001F;  { all the size attributes  }
       OT_NON_SIZE  = longint(not OT_SIZE_MASK);
 
       { Bits 8..11: modifiers }
@@ -87,6 +92,7 @@ interface
       otf_reg_mmx  = $02000000;
       otf_reg_xmm  = $04000000;
       otf_reg_ymm  = $08000000;
+      otf_reg_zmm  = $10000000;
 
       otf_reg_extra_mask = $0F000000;
       { Bits 16..19: subclasses, meaning depends on classes field }
@@ -96,7 +102,8 @@ interface
       otf_sub3     = $00080000;
       OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
 
-      OT_REG_EXTRA_MASK = $0F000000;
+      //OT_REG_EXTRA_MASK = $0F000000;
+      OT_REG_EXTRA_MASK = $1F000000;
 
       OT_REG_TYPMASK = otf_reg_cdt or otf_reg_gpr or otf_reg_sreg or otf_reg_extra_mask;
       { register class 0: CRx, DRx and TRx }
@@ -158,14 +165,21 @@ interface
       OT_XMEM32    = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS32;
       OT_XMEM64    = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS64;
 
-      { register class 5: XMM (both reg and r/m) }
+      { register class 5: YMM (both reg and r/m) }
       OT_YMMREG    = OT_REGNORM or otf_reg_ymm;
       OT_YMMRM     = OT_REGMEM or otf_reg_ymm;
       OT_YMEM32    = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS32;
       OT_YMEM64    = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS64;
 
+      { register class 5: ZMM (both reg and r/m) }
+      OT_ZMMREG    = OT_REGNORM or otf_reg_zmm;
+      OT_ZMMRM     = OT_REGMEM or otf_reg_zmm;
+      OT_ZMEM32    = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS32;
+      OT_ZMEM64    = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS64;
+
+
       { Vector-Memory operands }
-      OT_VMEM_ANY  = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64;
+      OT_VMEM_ANY  = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64 or OT_ZMEM32 or OT_ZMEM64;
 
       { Memory operands }
       OT_MEM8      = OT_MEMORY or OT_BITS8;
@@ -174,13 +188,14 @@ interface
       OT_MEM64     = OT_MEMORY or OT_BITS64;
       OT_MEM128    = OT_MEMORY or OT_BITS128;
       OT_MEM256    = OT_MEMORY or OT_BITS256;
+      OT_MEM512    = OT_MEMORY or OT_BITS512;
       OT_MEM80     = OT_MEMORY or OT_BITS80;
 
       OT_MEM_OFFS  = OT_MEMORY or otf_sub0;  { special type of EA  }
                                              { simple [address] offset  }
 
       { Matches any type of r/m operand }
-      OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM or OT_REG_EXTRA_MASK;
+      OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK;
 
       { Immediate operands }
       OT_IMM8      = OT_IMMEDIATE or OT_BITS8;
@@ -257,10 +272,10 @@ interface
 
       TMemRefSizeInfo = (msiUnkown, msiUnsupported, msiNoSize,
                          msiMultiple, msiMultiple8, msiMultiple16, msiMultiple32,
-                         msiMultiple64, msiMultiple128, msiMultiple256,
+                         msiMultiple64, msiMultiple128, msiMultiple256, msiMultiple512,
                          msiMemRegSize, msiMemRegx16y32, msiMemRegx32y64, msiMemRegx64y128, msiMemRegx64y256,
-                         msiMem8, msiMem16, msiMem32, msiMem64, msiMem128, msiMem256,
-                         msiXMem32, msiXMem64, msiYMem32, msiYMem64,
+                         msiMem8, msiMem16, msiMem32, msiMem64, msiMem128, msiMem256, msiMem512,
+                         msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64,
                          msiVMemMultiple, msiVMemRegSize);
 
       TConstSizeInfo  = (csiUnkown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64);
@@ -275,9 +290,11 @@ interface
       MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultiple8,
                                                  msiMultiple16, msiMultiple32,
                                                  msiMultiple64, msiMultiple128,
-                                                 msiMultiple256, msiVMemMultiple];
+                                                 msiMultiple256, msiMultiple512,
+                                                 msiVMemMultiple];
 
       MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64,
+                                                     msiZMem32, msiZMem64,
                                                      msiVMemMultiple, msiVMemRegSize];
 
       InsProp : array[tasmop] of TInsProp =
@@ -389,7 +406,8 @@ interface
       tinsentry=packed record
         opcode  : tasmop;
         ops     : byte;
-        optypes : array[0..max_operands-1] of longint;
+        //optypes : array[0..max_operands-1] of longint;
+        optypes : array[0..max_operands-1] of int64; //TG
         code    : array[0..maxinfolen] of char;
         flags   : tinsflags;
       end;
@@ -403,6 +421,8 @@ interface
          function calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;override;
       end;
 
+      { taicpu }
+
       taicpu = class(tai_cpu_abstract_sym)
          opsize    : topsize;
          constructor op_none(op : tasmop);
@@ -494,6 +514,7 @@ interface
          procedure write0x67prefix(objdata:TObjData);
          procedure Swapoperands;
          function  FindInsentry(objdata:TObjData):boolean;
+         function  CheckUseEVEX: boolean;
       end;
 
     function is_64_bit_ref(const ref:treference):boolean;
@@ -604,7 +625,8 @@ implementation
      const
 {$if defined(x86_64)}
        { Intel style operands ! }
-       opsize_2_type:array[0..2,topsize] of longint=(
+       //TG opsize_2_type:array[0..2,topsize] of longint=(
+         opsize_2_type:array[0..2,topsize] of int64=(
          (OT_NONE,
           OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
           OT_BITS16,OT_BITS32,OT_BITS64,
@@ -1097,6 +1119,7 @@ implementation
       var
         i : longint;
         s : string;
+        regnr: string;
         addsize : boolean;
       begin
         s:='['+std_op2str[opcode];
@@ -1110,11 +1133,20 @@ implementation
                 s:=s+',';
                { type }
                addsize:=false;
-               if (ot and OT_REG_EXTRA_MASK)=OT_XMMREG then
-                s:=s+'xmmreg'
+
+               regnr := '';
+               if getregtype(reg) = R_MMREGISTER then
+                str(getsupreg(reg),regnr);
+
+               if (ot and OT_XMMREG)=OT_XMMREG then
+                s:=s+'xmmreg' + regnr
                else
-                 if (ot and OT_REG_EXTRA_MASK)=OT_YMMREG then
-                  s:=s+'ymmreg'
+                 if (ot and OT_YMMREG)=OT_YMMREG then
+                  s:=s+'ymmreg' + regnr
+               else
+                 if (ot and OT_ZMMREG)=OT_ZMMREG then
+                  s:=s+'zmmreg' + regnr
+
                else
                  if (ot and OT_REG_EXTRA_MASK)=OT_MMXREG then
                   s:=s+'mmxreg'
@@ -1161,6 +1193,9 @@ implementation
                   else
                    if (ot and OT_BITS256)<>0 then
                     s:=s+'256'
+                   else
+                    if (ot and OT_BITS512)<>0 then
+                     s:=s+'512'
                   else
                     s:=s+'??';
                   { signed }
@@ -1330,14 +1365,16 @@ implementation
                       { create ot field }
                       if (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR = OT_REG_GPR) and
                          ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
-                          (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG)
+                          (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG) or
+                          (reg_ot_table[findreg_by_number(ref^.index)] = OT_ZMMREG)
                          ) then
                         // AVX2 - vector-memory-referenz (e.g. vgatherdpd xmm0, [rax  xmm1], xmm2)
                         ot := (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR) or
                               (reg_ot_table[findreg_by_number(ref^.index)])
                       else if (ref^.base = NR_NO) and
                               ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
-                               (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG)
+                               (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG) or
+                               (reg_ot_table[findreg_by_number(ref^.index)] = OT_ZMMREG)
                               ) then
                         // AVX2 - vector-memory-referenz without base-register (e.g. vgatherdpd xmm0, [xmm1], xmm2)
                         ot := (OT_REG_GPR) or
@@ -1495,7 +1532,7 @@ implementation
       }
       var
         insot,
-        currot,
+        currot: int64;
         i,j,asize,oprs : longint;
         insflags:tinsflags;
         siz : array[0..max_operands-1] of longint;
@@ -1610,13 +1647,15 @@ implementation
            begin
              insot:=p^.optypes[i];
              if ((insot and (OT_XMMRM or OT_REG_EXTRA_MASK)) = OT_XMMRM) OR
-                ((insot and (OT_YMMRM or OT_REG_EXTRA_MASK)) = OT_YMMRM) then
+                ((insot and (OT_YMMRM or OT_REG_EXTRA_MASK)) = OT_YMMRM) OR
+                ((insot and (OT_ZMMRM or OT_REG_EXTRA_MASK)) = OT_ZMMRM) then
              begin
                if (insot and OT_SIZE_MASK) = 0 then
                begin
-                 case insot and (OT_XMMRM or OT_YMMRM or OT_REG_EXTRA_MASK) of
+                 case insot and (OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of
                    OT_XMMRM: insot := insot or OT_BITS128;
                    OT_YMMRM: insot := insot or OT_BITS256;
+                   OT_ZMMRM: insot := insot or OT_BITS512;
                  end;
                end;
              end;
@@ -1670,10 +1709,18 @@ implementation
     function taicpu.FindInsentry(objdata:TObjData):boolean;
       var
         i : longint;
+
+        //TG TODO delete
+        p: pInsentry;
+
       begin
         result:=false;
       { Things which may only be done once, not when a second pass is done to
         optimize }
+
+        //TG TODO delete
+        p := Insentry;
+
         if (Insentry=nil) or (IF_PASS2 in InsEntry^.flags) then
          begin
            current_filepos:=fileinfo;
@@ -1713,6 +1760,23 @@ implementation
         inssize:=-1;
       end;
 
+    function taicpu.CheckUseEVEX: boolean;
+    var
+      i: integer;
+    begin
+      result := false;
+
+      for i := 0 to ops - 1 do
+      begin
+        if (oper[i]^.typ=top_reg) and
+           (getregtype(oper[i]^.reg) = R_MMREGISTER) then
+         if getsupreg(oper[i]^.reg)>=16 then
+          result := true;
+
+        //TG TODO k1 + z
+      end;
+    end;
+
 
     function taicpu.Pass1(objdata:TObjData):longint;
       begin
@@ -1987,7 +2051,8 @@ implementation
           (0, 1, 2, 3, 6, 7, 5, 4);
         maxsupreg: array[tregistertype] of tsuperregister=
 {$ifdef x86_64}
-          (0, 16, 9, 8, 16, 32, 0, 0);
+          //(0, 16, 9, 8, 16, 32, 0, 0);
+          (0, 16, 9, 8, 32, 32, 0, 0); //TG TODO check
 {$else x86_64}
           (0,  8, 9, 8,  8, 32, 0, 0);
 {$endif x86_64}
@@ -1997,8 +2062,10 @@ implementation
       begin
         rs:=getsupreg(r);
         rt:=getregtype(r);
+
         if (rs>=maxsupreg[rt]) then
-          badreg(r);
+         badreg(r);
+
         result:=rs and 7;
         if (rt=R_INTREGISTER) then
           begin
@@ -2028,11 +2095,17 @@ implementation
             AH/BH/CH/DH }
               result:=result or $80;
           R_MMREGISTER:
-            if getsupreg(r)>=RS_XMM8 then
+            //if getsupreg(r)>=RS_XMM8 then
+            // AVX512 = 32 register
+            //    rexbit = 0 => MMRegister 0..7  or 16..23
+            //    rexbit = 1 => MMRegister 8..15 or 24..31
+            if (getsupreg(r) and $08) = $08 then
               result:=result or $47;
         end;
       end;
 
+
+
     function process_ea_ref_64_32(const input:toper;var output:ea;rfield:longint):boolean;
       var
         sym   : tasmsymbol;
@@ -2077,7 +2150,7 @@ implementation
          begin
            { 16 bit? }
 
-           if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY]) and
+           if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY,R_SUBMMZ]) and
                (br<>NR_NO) and (bsub=R_SUBQ)
               ) then
            begin
@@ -2143,64 +2216,128 @@ implementation
              NR_RAX,
              NR_XMM0,
              NR_XMM8,
+             NR_XMM16,
+             NR_XMM24,
              NR_YMM0,
-             NR_YMM8  : index:=0;
+             NR_YMM8,
+             NR_YMM16,
+             NR_YMM24,
+             NR_ZMM0,
+             NR_ZMM8,
+             NR_ZMM16,
+             NR_ZMM24: index:=0;
              NR_R9D,
              NR_ECX,
              NR_R9,
              NR_RCX,
              NR_XMM1,
              NR_XMM9,
+             NR_XMM17,
+             NR_XMM25,
              NR_YMM1,
-             NR_YMM9  : index:=1;
+             NR_YMM9,
+             NR_YMM17,
+             NR_YMM25,
+             NR_ZMM1,
+             NR_ZMM9,
+             NR_ZMM17,
+             NR_ZMM25: index:=1;
              NR_R10D,
              NR_EDX,
              NR_R10,
              NR_RDX,
              NR_XMM2,
              NR_XMM10,
+             NR_XMM18,
+             NR_XMM26,
              NR_YMM2,
-             NR_YMM10 : index:=2;
+             NR_YMM10,
+             NR_YMM18,
+             NR_YMM26,
+             NR_ZMM2,
+             NR_ZMM10,
+             NR_ZMM18,
+             NR_ZMM26: index:=2;
              NR_R11D,
              NR_EBX,
              NR_R11,
              NR_RBX,
              NR_XMM3,
              NR_XMM11,
+             NR_XMM19,
+             NR_XMM27,
              NR_YMM3,
-             NR_YMM11 : index:=3;
+             NR_YMM11,
+             NR_YMM19,
+             NR_YMM27,
+             NR_ZMM3,
+             NR_ZMM11,
+             NR_ZMM19,
+             NR_ZMM27: index:=3;
              NR_R12D,
              NR_ESP,
              NR_R12,
              NR_NO,
              NR_XMM4,
              NR_XMM12,
+             NR_XMM20,
+             NR_XMM28,
              NR_YMM4,
-             NR_YMM12 : index:=4;
+             NR_YMM12,
+             NR_YMM20,
+             NR_YMM28,
+             NR_ZMM4,
+             NR_ZMM12,
+             NR_ZMM20,
+             NR_ZMM28: index:=4;
              NR_R13D,
              NR_EBP,
              NR_R13,
              NR_RBP,
              NR_XMM5,
              NR_XMM13,
+             NR_XMM21,
+             NR_XMM29,
              NR_YMM5,
-             NR_YMM13: index:=5;
+             NR_YMM13,
+             NR_YMM21,
+             NR_YMM29,
+             NR_ZMM5,
+             NR_ZMM13,
+             NR_ZMM21,
+             NR_ZMM29: index:=5;
              NR_R14D,
              NR_ESI,
              NR_R14,
              NR_RSI,
              NR_XMM6,
              NR_XMM14,
+             NR_XMM22,
+             NR_XMM30,
              NR_YMM6,
-             NR_YMM14: index:=6;
+             NR_YMM14,
+             NR_YMM22,
+             NR_YMM30,
+             NR_ZMM6,
+             NR_ZMM14,
+             NR_ZMM22,
+             NR_ZMM30: index:=6;
              NR_R15D,
              NR_EDI,
              NR_R15,
              NR_RDI,
              NR_XMM7,
              NR_XMM15,
+             NR_XMM23,
+             NR_XMM31,
              NR_YMM7,
-             NR_YMM15: index:=7;
+             NR_YMM15,
+             NR_YMM23,
+             NR_YMM31,
+             NR_ZMM7,
+             NR_ZMM15,
+             NR_ZMM23,
+             NR_ZMM31: index:=7;
            else
              exit;
            end;
@@ -2524,6 +2661,7 @@ implementation
         c     : byte;
         len     : shortint;
         ea_data : ea;
+        exists_evex: boolean;
         exists_vex: boolean;
         exists_vex_extension: boolean;
         exists_prefix_66: boolean;
@@ -2540,6 +2678,7 @@ implementation
         exists_prefix_66 := false;
         exists_prefix_F2 := false;
         exists_prefix_F3 := false;
+        exists_evex      := false;
 {$ifdef x86_64}
         rex:=0;
         omit_rexw:=false;
@@ -2708,11 +2847,12 @@ implementation
             &362: // VEX prefix for AVX (length = 2 or 3 bytes, dependens on REX.XBW or opcode-prefix ($0F38 or $0F3A))
                   // =>> DEFAULT = 2 Bytes
               begin
-                if not(exists_vex) then
-                begin
-                  inc(len, 2);
-                  exists_vex := true;
-                end;
+                //if not(exists_vex) then
+                //begin
+                //  inc(len, 2);
+                //end;
+
+                exists_vex := true;
               end;
             &363: // REX.W = 1
                   // =>> VEX prefix length = 3
@@ -2723,7 +2863,9 @@ implementation
                   exists_vex_extension := true;
                 end;
               end;
-            &364: ; // VEX length bit
+            &364: ; // VEX length bit 256
+            &351: ; // EVEX length bit 512
+            &352: ; // EVEX W1
             &366, // operand 2 (ymmreg) encoded immediate byte (bit 4-7)
             &367: inc(len); // operand 3 (ymmreg) encoded immediate byte (bit 4-7)
             &370: // VEX-Extension prefix $0F
@@ -2738,6 +2880,10 @@ implementation
                   exists_vex_extension := true;
                 end;
               end;
+            &350:
+              begin
+                exists_evex := true;
+              end;
             &300,&301,&302:
               begin
 {$if defined(x86_64) or defined(i8086)}
@@ -2760,14 +2906,47 @@ implementation
             else
               rex:=rex and $F7;
           end;
-        if not(exists_vex) then
+        if not(exists_vex or exists_evex) then
         begin
           if rex<>0 then
             Inc(len);
         end;
 {$endif}
-        if exists_vex then
+        if exists_evex and
+           exists_vex then
         begin
+          if CheckUseEVEX then
+          begin
+            inc(len, 4);
+          end
+          else
+          begin
+            inc(len, 2);
+            if exists_vex_extension then inc(len);
+
+            {$ifdef x86_64}
+              if not(exists_vex_extension) then
+              if rex and $0B <> 0 then inc(len);  // REX.WXB <> 0 =>> needed VEX-Extension
+            {$endif x86_64}
+          end;
+
+          if exists_prefix_66 then dec(len);
+          if exists_prefix_F2 then dec(len);
+          if exists_prefix_F3 then dec(len);
+
+        end
+        else if exists_evex then
+        begin
+          inc(len, 4);
+
+          if exists_prefix_66 then dec(len);
+          if exists_prefix_F2 then dec(len);
+          if exists_prefix_F3 then dec(len);
+        end
+        else
+        begin
+          if exists_vex then
+          begin
           if exists_prefix_66 then dec(len);
           if exists_prefix_F2 then dec(len);
           if exists_prefix_F3 then dec(len);
@@ -2777,6 +2956,8 @@ implementation
             if rex and $0B <> 0 then inc(len);  // REX.WXB <> 0 =>> needed VEX-Extension
   {$endif x86_64}
 
+          end;
+
         end;
         calcsize:=len;
       end;
@@ -2806,7 +2987,7 @@ implementation
       end;
 
 
-    procedure taicpu.GenCode(objdata:TObjData);
+        procedure taicpu.gencode(objdata: TObjData);
       {
        * the actual codes (C syntax, i.e. octal):
        * \0            - terminates the code. (Unless it's a literal of course.)
@@ -2863,18 +3044,25 @@ implementation
        * \333          - 0xF3 prefix for SSE instructions
        * \334          - 0xF2 prefix for SSE instructions
        * \335          - Indicates 64-bit operand size with REX.W not necessary
+
+       * \350          - EVEX prefix for AVX instructions
+       * \351          - EVEX Vector length 512
+       * \352          - EVEX W1
+
        * \361          - 0x66 prefix for SSE instructions
 
        * \362          - VEX prefix for AVX instructions
        * \363          - VEX W1
        * \364          - VEX Vector length 256
-       * \366          - operand 2 (ymmreg) encoded in bit 4-7 of the immediate byte
-       * \367          - operand 3 (ymmreg) encoded in bit 4-7 of the immediate byte
+
+       * \366          - operand 2 (ymmreg,zmmreg) encoded in bit 4-7 of the immediate byte
+       * \367          - operand 3 (ymmreg,zmmreg) encoded in bit 4-7 of the immediate byte
 
        * \370          - VEX 0F-FLAG
        * \371          - VEX 0F38-FLAG
        * \372          - VEX 0F3A-FLAG
 
+
       }
 
       var
@@ -3007,6 +3195,7 @@ implementation
          $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
          $0, $A, $A, $B, $8, $4);
       var
+        i: integer;
         c : byte;
         pb : pbyte;
         codes : pchar;
@@ -3017,13 +3206,40 @@ implementation
         relsym : TObjSymbol;
         needed_VEX_Extension: boolean;
         needed_VEX: boolean;
+        needed_EVEX: boolean;
         opmode: integer;
         VEXvvvv: byte;
         VEXmmmmm: byte;
+        VEXw    : byte;
+        VEXpp   : byte;
+        VEXll   : byte;
+        EVEXvvvv: byte;
+        EVEXpp: byte;
+        EVEXr: byte;
+        EVEXx: byte;
+        EVEXv: byte;
+        EVEXll: byte;
+        EVEXw0: byte;
+        EVEXw1: byte;
+        EVEXz   : byte;
+        EVEXaaa : byte;
+        EVEXb   : byte;
+        EVEXmm  : byte;
+
+        pins: tinsentry;
       begin
         { safety check }
+
+        //TG TODO delete
+        i := longword(insoffset);
+
         if objdata.currobjsec.size<>longword(insoffset) then
-           internalerror(200130121);
+        begin
+        //TG TODO delete
+          Message1(asmw_e_invalid_opcode_and_operands,GetString);
+
+          internalerror(200130121);
+        end;
 
         { those variables are initialized inside local procedures, the dfa cannot handle this yet }
         currsym:=nil;
@@ -3103,11 +3319,29 @@ implementation
 
         // needed VEX Prefix (for AVX etc.)
 
-        needed_VEX := false;
+        needed_VEX    := false;
+        needed_EVEX   := false;
         needed_VEX_Extension := false;
         opmode   := -1;
         VEXvvvv  := 0;
         VEXmmmmm := 0;
+
+        VEXll    := 0;
+        VEXw     := 0;
+        VEXpp    := 0;
+        EVEXpp   := 0;
+        EVEXvvvv := 0;
+        EVEXr    := 0;
+        EVEXx    := 0;
+        EVEXv    := 0;
+        EVEXll   := 0;
+        EVEXw0   := 0;
+        EVEXw1   := 0;
+        EVEXz    := 0;
+        EVEXaaa  := 0;
+        EVEXb    := 0;
+        EVEXmm   := 0;
+
         repeat
           c:=ord(codes^);
           inc(codes);
@@ -3117,32 +3351,93 @@ implementation
              &1,
              &2,
              &3: inc(codes,c);
+            &10,
+            &11,
+            &12: inc(codes, 1);
             &74: opmode := 0;
             &75: opmode := 1;
             &76: opmode := 2;
-           &333: VEXvvvv                := VEXvvvv  OR $02; // set SIMD-prefix $F3
-           &334: VEXvvvv                := VEXvvvv  OR $03; // set SIMD-prefix $F2
-           &361: VEXvvvv                := VEXvvvv  OR $01; // set SIMD-prefix $66
+     &100..&227: begin
+                   // AVX 512 - EVEX
+                   // check operands
+
+                   //TG TODO delete
+                   pins := insentry^;
+
+
+
+                   opidx := c and 7;
+                   if ops > opidx then
+                    if (oper[opidx]^.typ=top_reg) and
+                       (getregtype(oper[opidx]^.reg) = R_MMREGISTER) then
+                     if getsupreg(oper[opidx]^.reg) and $10 = $0 then EVEXr := 1;  //TG TODO check
+
+
+                   opidx := (c shr 3) and 7;
+                   if ops > opidx then
+                    if (oper[opidx]^.typ=top_reg) and
+                      (getregtype(oper[opidx]^.reg) = R_MMREGISTER) then
+                     if getsupreg(oper[opidx]^.reg) and $10 = $0 then EVEXx := 1;  //TG TODO check
+
+                 end;
+           &333: begin
+                   VEXvvvv              := VEXvvvv  OR $02; // set SIMD-prefix $F3
+                   VEXpp                := $02;             // set SIMD-prefix $F3
+                   EVEXpp               := $02;             // set SIMD-prefix $F3
+                 end;
+           &334: begin
+                   VEXvvvv              := VEXvvvv  OR $03; // set SIMD-prefix $F2
+                   VEXpp                := $03;             // set SIMD-prefix $F2
+                   EVEXpp               := $03;             // set SIMD-prefix $F2
+                 end;
+           &350: needed_EVEX            := true;            // AVX512 instruction or AVX128/256/512-instruction (depended on operands [x,y,z]mm16..)
+           &351: EVEXll                 := $02;             // vectorlength = 512 bits AND no scalar
+           &352: EVEXw1                 := $01;
+           &361: begin
+                   VEXvvvv              := VEXvvvv  OR $01; // set SIMD-prefix $66
+                   VEXpp                := $01;             // set SIMD-prefix $66
+                   EVEXpp               := $01;             // set SIMD-prefix $66
+                 end;
            &362: needed_VEX             := true;
            &363: begin
                    needed_VEX_Extension := true;
                    VEXvvvv              := VEXvvvv  OR (1 shl 7); // set REX.W
+                   VEXw                 := 1;
+                 end;
+           &364: begin
+                   VEXvvvv              := VEXvvvv  OR $04; // vectorlength = 256 bits AND no scalar
+                   VEXll                := $01;
+                   EVEXll               := $01;
+                 end;
+           &366,
+           &367: begin
+                   opidx:=c-&364;  { 0366->operand 2, 0367->operand 3 }
+                   if (ops > opidx) and
+                      (oper[opidx]^.typ=top_reg) and
+                      ((oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_xmm) or
+                       (oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_ymm) or
+                       (oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_zmm)) then
+                    if (getsupreg(oper[opidx]^.reg) and $10 = $0) then EVEXx := 1;  //TG TODO check
+                 end;
+           &370: begin
+                   VEXmmmmm             := VEXmmmmm OR $01; // set leading opcode byte $0F
+                   EVEXmm               := $01;
                  end;
-           &364: VEXvvvv                := VEXvvvv  OR $04; // vectorlength = 256 bits AND no scalar
-           &370: VEXmmmmm               := VEXmmmmm OR $01; // set leading opcode byte $0F
            &371: begin
                    needed_VEX_Extension := true;
                    VEXmmmmm             := VEXmmmmm OR $02; // set leading opcode byte $0F38
+                   EVEXmm               := $02;
                  end;
            &372: begin
                    needed_VEX_Extension := true;
                    VEXmmmmm             := VEXmmmmm OR $03; // set leading opcode byte $0F3A
+                   EVEXmm               := $03;
                  end;
 
           end;
         until false;
 
-        if needed_VEX then
+        if needed_VEX or needed_EVEX then
         begin
           if (opmode > ops) or
              (opmode < -1) then
@@ -3151,14 +3446,19 @@ implementation
           end
           else if opmode = -1 then
           begin
-            VEXvvvv := VEXvvvv or ($0F shl 3); // set VEXvvvv bits (bits 6-3) to 1
+            VEXvvvv  := VEXvvvv or ($0F shl 3); // set VEXvvvv bits (bits 6-3) to 1
+            EVEXvvvv := $0F; //TG TODO check
           end
           else if oper[opmode]^.typ = top_reg then
           begin
-            VEXvvvv := VEXvvvv or ((not(regval(oper[opmode]^.reg)) and $07) shl 3);
+            VEXvvvv  := VEXvvvv or ((not(regval(oper[opmode]^.reg)) and $07) shl 3);
+            EVEXvvvv := not(regval(oper[opmode]^.reg)) and $07;
 
             {$ifdef x86_64}
               if rexbits(oper[opmode]^.reg) = 0 then VEXvvvv := VEXvvvv or (1 shl 6);
+
+              if rexbits(oper[opmode]^.reg) = 0 then EVEXvvvv := EVEXvvvv or (1 shl 3);
+              if getsupreg(oper[opmode]^.reg) and $10 = 0 then EVEXv := 1;  //TG TODO check
             {$else}
               VEXvvvv := VEXvvvv or (1 shl 6);
             {$endif x86_64}
@@ -3172,7 +3472,55 @@ implementation
             {$endif x86_64}
           end;
 
-          if needed_VEX_Extension then
+          //TG
+          if needed_EVEX and needed_VEX then
+          begin
+            needed_EVEX := false;
+
+            //if (EVEXr and EVEXv and EVEXx) = 0 then
+            if CheckUseEVEX then
+            begin
+              // EVEX-Flags r,v,x indicate extended-MMregister
+              // Flag = 0 =>> [x,y,z]mm16..[x,y,z]mm31
+              // Flag = 1 =>> [x,y,z]mm00..[x,y,z]mm15
+
+              needed_EVEX := true;
+
+              needed_VEX := false;
+              needed_VEX_Extension := false;  //TG TODO check
+
+              //TG TODO Dest-Register-Extention {k1..k7} or {z}
+              //        Broadcast  Disp
+            end;
+          end;
+
+          if needed_EVEX then
+          begin
+
+
+            bytes[0] := $62;
+
+            i := rex and 7;
+            //bytes[1] := ((VEXmmmmm and $03) shl 0)  or ((not(rex) and $07) shl 4) and EVEXr and EVEXb;
+            bytes[1] := ((EVEXmm   and $03) shl 0)  or
+                        ((not(rex) and $07) shl 5)  or
+                        ((EVEXr    and $01) shl 4) ; // or
+                        //((EVEXx    and $01) shl 6);
+
+            bytes[2] := ((EVEXpp   and $03) shl 0)  or
+                        ((1        and $01) shl 2)  or  // fixed in AVX512
+                        ((EVEXvvvv and $0F) shl 3)  or
+                        ((EVEXw1   and $01) shl 7);
+
+            bytes[3] := ((EVEXaaa  and $07) shl 0)  or
+                        ((EVEXv    and $01) shl 3)  or
+                        ((EVEXb    and $01) shl 4)  or
+                        ((EVEXll   and $03) shl 5)  or
+                        ((EVEXz    and $01) shl 7);
+
+            objdata.writebytes(bytes,4);
+          end
+          else if needed_VEX_Extension then
           begin
             // VEX-Prefix-Length = 3 Bytes
             {$ifdef x86_64}
@@ -3208,6 +3556,22 @@ implementation
           opmode := -1;
         end;
 
+        if not(needed_EVEX) then
+        begin
+          for opidx := 0 to ops - 1 do
+          begin
+            if ops > opidx then
+             if (oper[opidx]^.typ=top_reg) and
+                (getregtype(oper[opidx]^.reg) = R_MMREGISTER) then
+              if getsupreg(oper[opidx]^.reg) and $10 = $10 then
+              begin
+                Message1(asmw_e_invalid_opcode_and_operands,GetString);
+                break;
+              end;
+              //badreg(oper[opidx]^.reg);
+          end;
+        end;
+
         { load data to write }
         codes:=insentry^.code;
 
@@ -3220,7 +3584,7 @@ implementation
             &1,&2,&3 :
               begin
 {$ifdef x86_64}
-                if not(needed_VEX) then  // TG
+                if not(needed_VEX or needed_EVEX) then  // TG
                   maybewriterex;
 {$endif x86_64}
                 objdata.writebytes(codes^,c);
@@ -3262,7 +3626,7 @@ implementation
             &10,&11,&12 :
               begin
 {$ifdef x86_64}
-                if not(needed_VEX) then  // TG
+                if not(needed_VEX or needed_EVEX) then  // TG
                   maybewriterex;
 {$endif x86_64}
                 bytes[0]:=ord(codes^)+regval(oper[c-&10]^.reg);
@@ -3519,7 +3883,7 @@ implementation
             &361:
               begin
 {$ifndef i8086}
-                if not(needed_VEX) then
+                if not(needed_VEX or needed_EVEX) then
                   write0x66prefix(objdata);
 {$endif not i8086}
               end;
@@ -3531,7 +3895,7 @@ implementation
               end;
             &333 :
               begin
-                if not(needed_VEX) then
+                if not(needed_VEX or needed_EVEX) then
                 begin
                   bytes[0]:=$f3;
                   objdata.writebytes(bytes,1);
@@ -3539,7 +3903,7 @@ implementation
               end;
             &334 :
               begin
-                if not(needed_VEX) then
+                if not(needed_VEX or needed_EVEX) then
                 begin
                   bytes[0]:=$f2;
                   objdata.writebytes(bytes,1);
@@ -3558,11 +3922,14 @@ implementation
             &366, &367:
               begin
                 opidx:=c-&364;  { 0366->operand 2, 0367->operand 3 }
-                if needed_VEX and
+                if (needed_VEX or needed_EVEX) and
                   (ops=4) and
                   (oper[opidx]^.typ=top_reg) and
-                  ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_xmm) or
-                  ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_ymm) then
+                  (
+                   ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_xmm) or
+                   ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_ymm) or
+                   ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_zmm)
+                  ) then
                   begin
                     bytes[0] := ((getsupreg(oper[opidx]^.reg) and 15) shl 4);
                     objdata.writebytes(bytes,1);
@@ -3570,6 +3937,7 @@ implementation
                 else
                   Internalerror(2014032001);
               end;
+            &350..&352: ; // EVEX flags =>> nothing todo
             &370..&372: ; // VEX flags =>> nothing todo
             &37:
               begin
@@ -3586,7 +3954,7 @@ implementation
               begin
                 { rex should be written at this point }
 {$ifdef x86_64}
-                if not(needed_VEX) then  // TG
+                if not(needed_VEX or needed_EVEX) then  // TG
                   if (rex<>0) and not(rexwritten) then
                     internalerror(200603191);
 {$endif x86_64}
@@ -3998,6 +4366,7 @@ implementation
       RegMMXSizeMask: int64;
       RegXMMSizeMask: int64;
       RegYMMSizeMask: int64;
+      RegZMMSizeMask: int64;
 
       bitcount: integer;
 
@@ -4036,6 +4405,7 @@ implementation
           RegMMXSizeMask := 0;
           RegXMMSizeMask := 0;
           RegYMMSizeMask := 0;
+          RegZMMSizeMask := 0;
 
           while (insentry^.opcode=AsmOp) do
           begin
@@ -4061,15 +4431,19 @@ implementation
               if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR
                  ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR
                  ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR
-                 ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) then
+                 ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) OR
+                 ((insentry^.optypes[j] and OT_ZMEM32) = OT_ZMEM32) OR
+                 ((insentry^.optypes[j] and OT_ZMEM64) = OT_ZMEM64) then
               begin
                 inc(actVMemCount);
 
-                case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64) of
+                case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64 OR OT_ZMEM32 OR OT_ZMEM64) of
                   OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32;
                   OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64;
                   OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32;
                   OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64;
+                  OT_ZMEM32: actVMemTypes := actVMemTypes or OT_ZMEM32;
+                  OT_ZMEM64: actVMemTypes := actVMemTypes or OT_ZMEM64;
                         else InternalError(777206);
                 end;
               end
@@ -4080,7 +4454,7 @@ implementation
                   NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK);
                   if NewRegSize = 0 then
                     begin
-                      case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_REG_EXTRA_MASK) of
+                      case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of
                         OT_MMXREG: begin
                                      NewRegSize := OT_BITS64;
                                    end;
@@ -4092,12 +4466,17 @@ implementation
                                      NewRegSize := OT_BITS256;
                                      InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
                                    end;
+                        OT_ZMMREG: begin
+                                     NewRegSize := OT_BITS512;
+                                     InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
+                                   end;
+
                               else NewRegSize := not(0);
                       end;
                   end;
 
                 actRegSize  := actRegSize or NewRegSize;
-                actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_REG_EXTRA_MASK));
+                actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK));
                 end
               else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then
                 begin
@@ -4149,6 +4528,8 @@ implementation
                     OT_XMEM64: MRefInfo := msiXMem64;
                     OT_YMEM32: MRefInfo := msiYMem32;
                     OT_YMEM64: MRefInfo := msiYMem64;
+                    OT_ZMEM32: MRefInfo := msiZMem32;
+                    OT_ZMEM64: MRefInfo := msiZMem64;
                           else InternalError(777208);
                   end;
 
@@ -4158,6 +4539,8 @@ implementation
                                  msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128;
                                  msiYMem32,
                                  msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256;
+                                 msiZMem32,
+                                 msiZMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS512;
                                        else InternalError(777210);
                                end;
                     OT_YMMREG: case MRefInfo of
@@ -4165,8 +4548,20 @@ implementation
                                  msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128;
                                  msiYMem32,
                                  msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256;
+                                 msiZMem32,
+                                 msiZMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS512;
                                        else InternalError(777211);
                                end;
+                    OT_ZMMREG: case MRefInfo of
+                                 msiXMem32,
+                                 msiXMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS128;
+                                 msiYMem32,
+                                 msiYMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS256;
+                                 msiZMem32,
+                                 msiZMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS512;
+                                       else InternalError(777211);
+                               end;
+
                           //else InternalError(777209);
                   end;
 
@@ -4177,7 +4572,7 @@ implementation
                   end
                   else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then
                   begin
-                    if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64] then
+                    if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64] then
                     begin
                       InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple;
                     end
@@ -4196,10 +4591,11 @@ implementation
                 0: ; // nothing todo
                 1: begin
                      MRefInfo := msiUnkown;
-                     case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_REG_EXTRA_MASK) of
+                     case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of
                        OT_MMXRM: actMemSize := actMemSize or OT_BITS64;
                        OT_XMMRM: actMemSize := actMemSize or OT_BITS128;
                        OT_YMMRM: actMemSize := actMemSize or OT_BITS256;
+                       OT_ZMMRM: actMemSize := actMemSize or OT_BITS512;
                      end;
 
                      case actMemSize of
@@ -4210,6 +4606,7 @@ implementation
                        OT_BITS64: MRefInfo := msiMem64;
                        OT_BITS128: MRefInfo := msiMem128;
                        OT_BITS256: MRefInfo := msiMem256;
+                       OT_BITS512: MRefInfo := msiMem512;
                        OT_BITS80,
                        OT_FAR,
                        OT_NEAR,
@@ -4237,16 +4634,18 @@ implementation
                            else if ((MemRefSize = msiMem64)  OR (MRefInfo = msiMem64))  then MemRefSize := msiMultiple64
                            else if ((MemRefSize = msiMem128) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultiple128
                            else if ((MemRefSize = msiMem256) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultiple256
+                           else if ((MemRefSize = msiMem512) OR (MRefInfo = msiMem512)) then MemRefSize := msiMultiple512
                            else MemRefSize := msiMultiple;
                          end;
                      end;
 
                      if actRegCount > 0 then
                        begin
-                         case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_REG_EXTRA_MASK) of
+                         case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of
                            OT_MMXREG: RegMMXSizeMask := RegMMXSizeMask or actMemSize;
                            OT_XMMREG: RegXMMSizeMask := RegXMMSizeMask or actMemSize;
                            OT_YMMREG: RegYMMSizeMask := RegYMMSizeMask or actMemSize;
+                           OT_ZMMREG: RegZMMSizeMask := RegZMMSizeMask or actMemSize;
                                  else begin
                                         RegMMXSizeMask := not(0);
                                         RegXMMSizeMask := not(0);
@@ -4299,6 +4698,9 @@ implementation
                             end
                             else InternalError(777205);
                           end;
+
+                // TG TODO
+
             end;
           end;
         end;
diff --git a/compiler/x86/agx86int.pas b/compiler/x86/agx86int.pas
index 2857449084..2bb57d1d1c 100644
--- a/compiler/x86/agx86int.pas
+++ b/compiler/x86/agx86int.pas
@@ -386,6 +386,7 @@ implementation
                              writer.AsmWrite('word ptr ');
                      S_XMM: writer.AsmWrite('xmmword ptr ');
                      S_YMM: writer.AsmWrite('ymmword ptr ');
+                     S_ZMM: writer.AsmWrite('zmmword ptr ');
 {$ifdef x86_64}
                      S_BQ : if dest then
                              writer.AsmWrite('qword ptr ')
diff --git a/compiler/x86/cpubase.pas b/compiler/x86/cpubase.pas
index 646116ffcf..532183e7c9 100644
--- a/compiler/x86/cpubase.pas
+++ b/compiler/x86/cpubase.pas
@@ -589,8 +589,18 @@ implementation
         { for the name the sub reg doesn't matter }
         hr:=r;
         if (getregtype(hr)=R_MMREGISTER) and
-           (getsubreg(hr)<>R_SUBMMY) then
+           (getsubreg(hr)<>R_SUBMMY) and
+           (getsubreg(hr)<>R_SUBMMZ) then
           setsubreg(hr,R_SUBMMX);
+
+        //// TG TODO check
+        //if (getregtype(hr)=R_MMREGISTER) then
+        // case getsubreg(hr) of
+        //   R_SUBMMX: setsubreg(hr,R_SUBMMX);
+        //   R_SUBMMY: setsubreg(hr,R_SUBMMY);
+        //   R_SUBMMZ: setsubreg(hr,R_SUBMMZ);
+        //  else setsubreg(hr,R_SUBMMX);
+        // end;
         result:=findreg_by_number_table(hr,regnumber_index);
       end;
 
diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas
index b40ac83f95..48d09a6f0c 100644
--- a/compiler/x86/rax86.pas
+++ b/compiler/x86/rax86.pas
@@ -195,6 +195,7 @@ begin
   case _size of
     16: size := OS_M128;
     32: size := OS_M256;
+    64: size := OS_M512;
   end;
 
 {$ifdef i8086}
@@ -420,6 +421,7 @@ begin
                                S_Q   : memrefsize := 64;
                                S_XMM : memrefsize := 128;
                                S_YMM : memrefsize := 256;
+                               S_ZMM : memrefsize := 512;
                                   else Internalerror(777200);
                              end;
                              break;
@@ -579,6 +581,21 @@ begin
 
                                Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"256 bit memory operand"');
                              end;
+                    msiMem512:
+                             begin
+                               tx86operand(operands[i]).opsize := S_ZMM;
+                               tx86operand(operands[i]).size   := OS_M512;
+                               opsize := S_ZMM;
+                             end;
+                    msiMultiple512:
+                             begin
+                               tx86operand(operands[i]).opsize := S_ZMM;
+                               tx86operand(operands[i]).size   := OS_M512;
+                               opsize := S_ZMM;
+
+                               Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"512 bit memory operand"');
+                             end;
+
                   msiMemRegSize:
                              begin
                                // mem-ref-size = register size
@@ -750,7 +767,9 @@ begin
                         // in this case is we need the old handling ("S_NO")
                         // =>> ignore
                         if (tx86operand(operands[operand2]).opsize <> S_XMM) and
-                           (tx86operand(operands[operand2]).opsize <> S_YMM) then
+                           (tx86operand(operands[operand2]).opsize <> S_YMM) and
+                           (tx86operand(operands[operand2]).opsize <> S_ZMM) then
+
                           tx86operand(operands[i]).opsize:=tx86operand(operands[operand2]).opsize
                         else tx86operand(operands[operand2]).opsize := S_NO;
                       end;
diff --git a/compiler/x86/rax86int.pas b/compiler/x86/rax86int.pas
index 79ca23113d..5d839ff400 100644
--- a/compiler/x86/rax86int.pas
+++ b/compiler/x86/rax86int.pas
@@ -43,7 +43,7 @@ Unit Rax86int;
        {------------------ Assembler directives --------------------}
       AS_ALIGN,AS_DB,AS_DW,AS_DD,AS_DQ,AS_PUBLIC,AS_END,
        {------------------ Assembler Operators  --------------------}
-      AS_BYTE,AS_WORD,AS_DWORD,AS_QWORD,AS_TBYTE,AS_DQWORD,AS_OWORD,AS_XMMWORD,AS_YWORD,AS_YMMWORD,AS_NEAR,AS_FAR,
+      AS_BYTE,AS_WORD,AS_DWORD,AS_QWORD,AS_TBYTE,AS_DQWORD,AS_OWORD,AS_XMMWORD,AS_YWORD,AS_YMMWORD,AS_ZWORD,AS_ZMMWORD,AS_NEAR,AS_FAR,
       AS_HIGH,AS_LOW,AS_OFFSET,AS_SIZEOF,AS_VMTOFFSET,AS_SEG,AS_TYPE,AS_PTR,AS_MOD,AS_SHL,AS_SHR,AS_NOT,
       AS_AND,AS_OR,AS_XOR,AS_WRT,AS___GOTPCREL,AS_TARGET_DIRECTIVE);
 
@@ -143,7 +143,7 @@ Unit Rax86int;
        { problems with shl,shr,not,and,or and xor, they are }
        { context sensitive.                                 }
        _asmoperators : array[firstoperator..lastoperator] of tasmkeyword = (
-        'BYTE','WORD','DWORD','QWORD','TBYTE','DQWORD','OWORD','XMMWORD','YWORD','YMMWORD','NEAR','FAR','HIGH',
+        'BYTE','WORD','DWORD','QWORD','TBYTE','DQWORD','OWORD','XMMWORD','YWORD','YMMWORD','ZWORD','ZMMWORD','NEAR','FAR','HIGH',
         'LOW','OFFSET','SIZEOF','VMTOFFSET','SEG','TYPE','PTR','MOD','SHL','SHR','NOT','AND',
         'OR','XOR','WRT','GOTPCREL');
 
@@ -153,11 +153,12 @@ Unit Rax86int;
         ')',':','.','+','-','*',
         ';','identifier','register','opcode','/',
         '','','','','','','END',
-        '','','','','','','','','','','','',
+        '','','','','','','','','','','','','','',
         '','','','sizeof','vmtoffset','','type','ptr','mod','shl','shr','not',
         'and','or','xor','wrt','..gotpcrel',''
       );
 
+
     constructor tx86intreader.create;
       var
         i : tasmop;
@@ -261,6 +262,15 @@ Unit Rax86int;
           begin
             is_register:=true;
             actasmtoken:=AS_REGISTER;
+
+            //TG TODO CHECK
+            if getregtype(actasmregister) = R_MMREGISTER then
+            begin
+//                      actasmpattern:=actasmpattern + c;
+//                       c:=current_scanner.asmgetchar;
+            end;
+
+
           end;
       end;
 
@@ -1012,7 +1022,7 @@ Unit Rax86int;
         while (actasmtoken=AS_DOT) do
          begin
            Consume(AS_DOT);
-           if actasmtoken in [AS_BYTE,AS_ID,AS_WORD,AS_DWORD,AS_QWORD,AS_OWORD,AS_XMMWORD,AS_YWORD,AS_YMMWORD,AS_REGISTER] then
+           if actasmtoken in [AS_BYTE,AS_ID,AS_WORD,AS_DWORD,AS_QWORD,AS_OWORD,AS_XMMWORD,AS_YWORD,AS_YMMWORD,AS_ZWORD,AS_ZMMWORD,AS_REGISTER] then
              begin
                s:=s+'.'+actasmpattern;
                consume(actasmtoken);
@@ -2363,7 +2373,10 @@ Unit Rax86int;
             AS_OWORD,
             AS_XMMWORD,
             AS_YWORD,
-            AS_YMMWORD:
+            AS_YMMWORD,
+            AS_ZWORD,
+            AS_ZMMWORD
+            :
               begin
                 { Type specifier }
                 oper.hastype:=true;
@@ -2379,6 +2392,8 @@ Unit Rax86int;
                   AS_XMMWORD: oper.typesize:=16; 
                   AS_YWORD,                     
                   AS_YMMWORD: oper.typesize:=32;
+                  AS_ZWORD,
+                  AS_ZMMWORD: oper.typesize:=64;
                   else
                     internalerror(2010061101);
                 end;
diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat
index c5dc33b3ad..c11cbbae98 100644
--- a/compiler/x86/x86ins.dat
+++ b/compiler/x86/x86ins.dat
@@ -4513,8 +4513,9 @@ ymmreg,ymmreg,ymmrm                  \361\362\364\370\1\xD4\75\120        AVX2
 
 [VPADDSB]
 (Ch_Rop1, Ch_Rop2, Ch_Wop3)
-xmmreg,xmmreg,xmmrm                  \361\362\370\1\xEC\75\120            AVX,SANDYBRIDGE
-ymmreg,ymmreg,ymmrm                  \361\362\364\370\1\xEC\75\120        AVX2
+xmmreg,xmmreg,xmmrm                  \350\361\362\370\1\xEC\75\120            AVX,SANDYBRIDGE
+ymmreg,ymmreg,ymmrm                  \350\361\362\364\370\1\xEC\75\120        AVX2
+zmmreg,zmmreg,zmmrm                  \350\351\361\370\1\xEC\75\120            AVX2
 
 [VPADDSW]
 (Ch_Rop1, Ch_Rop2, Ch_Wop3)
diff --git a/compiler/x86/x86reg.dat b/compiler/x86/x86reg.dat
index 609a4828bb..50a785898c 100644
--- a/compiler/x86/x86reg.dat
+++ b/compiler/x86/x86reg.dat
@@ -159,6 +159,23 @@ NR_XMM12,$040C000c,xmm12,%xmm12,xmm12,xmm12,-1,-1,29,OT_XMMREG,4,64
 NR_XMM13,$040C000d,xmm13,%xmm13,xmm13,xmm13,-1,-1,30,OT_XMMREG,5,64
 NR_XMM14,$040C000e,xmm14,%xmm14,xmm14,xmm14,-1,-1,31,OT_XMMREG,6,64
 NR_XMM15,$040C000f,xmm15,%xmm15,xmm15,xmm15,-1,-1,32,OT_XMMREG,7,64
+NR_XMM16,$040C0010,xmm16,%xmm16,xmm16,xmm16,-1,-1,33,OT_XMMREG,0,64
+NR_XMM17,$040C0011,xmm17,%xmm17,xmm17,xmm17,-1,-1,34,OT_XMMREG,1,64
+NR_XMM18,$040C0012,xmm18,%xmm18,xmm18,xmm18,-1,-1,35,OT_XMMREG,2,64
+NR_XMM19,$040C0013,xmm19,%xmm19,xmm19,xmm19,-1,-1,36,OT_XMMREG,3,64
+NR_XMM20,$040C0014,xmm20,%xmm20,xmm20,xmm20,-1,-1,37,OT_XMMREG,4,64
+NR_XMM21,$040C0015,xmm21,%xmm21,xmm21,xmm21,-1,-1,38,OT_XMMREG,5,64
+NR_XMM22,$040C0016,xmm22,%xmm22,xmm22,xmm22,-1,-1,39,OT_XMMREG,6,64
+NR_XMM23,$040C0017,xmm23,%xmm23,xmm23,xmm23,-1,-1,40,OT_XMMREG,7,64
+NR_XMM24,$040C0018,xmm24,%xmm24,xmm24,xmm24,-1,-1,41,OT_XMMREG,0,64
+NR_XMM25,$040C0019,xmm25,%xmm25,xmm25,xmm25,-1,-1,42,OT_XMMREG,1,64
+NR_XMM26,$040C001A,xmm26,%xmm26,xmm26,xmm26,-1,-1,43,OT_XMMREG,2,64
+NR_XMM27,$040C001B,xmm27,%xmm27,xmm27,xmm27,-1,-1,44,OT_XMMREG,3,64
+NR_XMM28,$040C001C,xmm28,%xmm28,xmm28,xmm28,-1,-1,45,OT_XMMREG,4,64
+NR_XMM29,$040C001D,xmm29,%xmm29,xmm29,xmm29,-1,-1,46,OT_XMMREG,5,64
+NR_XMM30,$040C001E,xmm30,%xmm30,xmm30,xmm30,-1,-1,47,OT_XMMREG,6,64
+NR_XMM31,$040C001F,xmm31,%xmm31,xmm31,xmm31,-1,-1,48,OT_XMMREG,7,64
+
 
 NR_YMM0,$040D0000,ymm0,%ymm0,ymm0,ymm0,21,21,17,OT_YMMREG,0
 NR_YMM1,$040D0001,ymm1,%ymm1,ymm1,ymm1,22,22,18,OT_YMMREG,1
@@ -176,3 +193,54 @@ NR_YMM12,$040D000c,ymm12,%ymm12,ymm12,ymm12,-1,-1,29,OT_YMMREG,4,64
 NR_YMM13,$040D000d,ymm13,%ymm13,ymm13,ymm13,-1,-1,30,OT_YMMREG,5,64
 NR_YMM14,$040D000e,ymm14,%ymm14,ymm14,ymm14,-1,-1,31,OT_YMMREG,6,64
 NR_YMM15,$040D000f,ymm15,%ymm15,ymm15,ymm15,-1,-1,32,OT_YMMREG,7,64
+NR_YMM16,$040D0010,ymm16,%ymm16,ymm16,ymm16,-1,-1,33,OT_YMMREG,0,64
+NR_YMM17,$040D0011,ymm17,%ymm17,ymm17,ymm17,-1,-1,34,OT_YMMREG,1,64
+NR_YMM18,$040D0012,ymm18,%ymm18,ymm18,ymm18,-1,-1,35,OT_YMMREG,2,64
+NR_YMM19,$040D0013,ymm19,%ymm19,ymm19,ymm19,-1,-1,36,OT_YMMREG,3,64
+NR_YMM20,$040D0014,ymm20,%ymm20,ymm20,ymm20,-1,-1,37,OT_YMMREG,4,64
+NR_YMM21,$040D0015,ymm21,%ymm21,ymm21,ymm21,-1,-1,38,OT_YMMREG,5,64
+NR_YMM22,$040D0016,ymm22,%ymm22,ymm22,ymm22,-1,-1,39,OT_YMMREG,6,64
+NR_YMM23,$040D0017,ymm23,%ymm23,ymm23,ymm23,-1,-1,40,OT_YMMREG,7,64
+NR_YMM24,$040D0018,ymm24,%ymm24,ymm24,ymm24,-1,-1,41,OT_YMMREG,0,64
+NR_YMM25,$040D0019,ymm25,%ymm25,ymm25,ymm25,-1,-1,42,OT_YMMREG,1,64
+NR_YMM26,$040D001a,ymm26,%ymm26,ymm26,ymm26,-1,-1,43,OT_YMMREG,2,64
+NR_YMM27,$040D001b,ymm27,%ymm27,ymm27,ymm27,-1,-1,44,OT_YMMREG,3,64
+NR_YMM28,$040D001c,ymm28,%ymm28,ymm28,ymm28,-1,-1,45,OT_YMMREG,4,64
+NR_YMM29,$040D001d,ymm29,%ymm29,ymm29,ymm29,-1,-1,46,OT_YMMREG,5,64
+NR_YMM30,$040D001e,ymm30,%ymm30,ymm30,ymm30,-1,-1,47,OT_YMMREG,6,64
+NR_YMM31,$040D001f,ymm31,%ymm31,ymm31,ymm31,-1,-1,48,OT_YMMREG,7,64
+
+
+NR_ZMM0,$040E0000,zmm0,%zmm0,zmm0,zmm0,21,21,17,OT_ZMMREG,0
+NR_ZMM1,$040E0001,zmm1,%zmm1,zmm1,zmm1,22,22,18,OT_ZMMREG,1
+NR_ZMM2,$040E0002,zmm2,%zmm2,zmm2,zmm2,23,23,19,OT_ZMMREG,2
+NR_ZMM3,$040E0003,zmm3,%zmm3,zmm3,zmm3,24,24,20,OT_ZMMREG,3
+NR_ZMM4,$040E0004,zmm4,%zmm4,zmm4,zmm4,25,25,21,OT_ZMMREG,4
+NR_ZMM5,$040E0005,zmm5,%zmm5,zmm5,zmm5,26,26,22,OT_ZMMREG,5
+NR_ZMM6,$040E0006,zmm6,%zmm6,zmm6,zmm6,27,27,23,OT_ZMMREG,6
+NR_ZMM7,$040E0007,zmm7,%zmm7,zmm7,zmm7,28,28,24,OT_ZMMREG,7
+NR_ZMM8,$040E0008,zmm8,%zmm8,zmm8,zmm8,-1,-1,25,OT_ZMMREG,0,64
+NR_ZMM9,$040E0009,zmm9,%zmm9,zmm9,zmm9,-1,-1,26,OT_ZMMREG,1,64
+NR_ZMM10,$040E000A,zmm10,%zmm10,zmm10,zmm10,-1,-1,27,OT_ZMMREG,2,64
+NR_ZMM11,$040E000B,zmm11,%zmm11,zmm11,zmm11,-1,-1,28,OT_ZMMREG,3,64
+NR_ZMM12,$040E000C,zmm12,%zmm12,zmm12,zmm12,-1,-1,29,OT_ZMMREG,4,64
+NR_ZMM13,$040E000D,zmm13,%zmm13,zmm13,zmm13,-1,-1,30,OT_ZMMREG,5,64
+NR_ZMM14,$040E000E,zmm14,%zmm14,zmm14,zmm14,-1,-1,31,OT_ZMMREG,6.64
+NR_ZMM15,$040E000F,zmm15,%zmm15,zmm15,zmm15,-1,-1,32,OT_ZMMREG,7,64
+NR_ZMM16,$040E0010,zmm16,%zmm16,zmm16,zmm16,-1,-1,33,OT_ZMMREG,0,64
+NR_ZMM17,$040E0011,zmm17,%zmm17,zmm17,zmm17,-1,-1,34,OT_ZMMREG,1,64
+NR_ZMM18,$040E0012,zmm18,%zmm18,zmm18,zmm18,-1,-1,35,OT_ZMMREG,2,64
+NR_ZMM19,$040E0013,zmm19,%zmm19,zmm19,zmm19,-1,-1,36,OT_ZMMREG,3,64
+NR_ZMM20,$040E0014,zmm20,%zmm20,zmm20,zmm20,-1,-1,37,OT_ZMMREG,4,64
+NR_ZMM21,$040E0015,zmm21,%zmm21,zmm21,zmm21,-1,-1,38,OT_ZMMREG,5,64
+NR_ZMM22,$040E0016,zmm22,%zmm22,zmm22,zmm22,-1,-1,39,OT_ZMMREG,6,64
+NR_ZMM23,$040E0017,zmm23,%zmm23,zmm23,zmm23,-1,-1,40,OT_ZMMREG,7,64
+NR_ZMM24,$040E0018,zmm24,%zmm24,zmm24,zmm24,-1,-1,41,OT_ZMMREG,0,64
+NR_ZMM25,$040E0019,zmm25,%zmm25,zmm25,zmm25,-1,-1,42,OT_ZMMREG,1,64
+NR_ZMM26,$040E001A,zmm26,%zmm26,zmm26,zmm26,-1,-1,43,OT_ZMMREG,2,64
+NR_ZMM27,$040E001B,zmm27,%zmm27,zmm27,zmm27,-1,-1,44,OT_ZMMREG,3,64
+NR_ZMM28,$040E001C,zmm28,%zmm28,zmm28,zmm28,-1,-1,45,OT_ZMMREG,4,64
+NR_ZMM29,$040E001D,zmm29,%zmm29,zmm29,zmm29,-1,-1,46,OT_ZMMREG,5,64
+NR_ZMM30,$040E001E,zmm30,%zmm30,zmm30,zmm30,-1,-1,47,OT_ZMMREG,6,64
+NR_ZMM31,$040E001F,zmm31,%zmm31,zmm31,zmm31,-1,-1,48,OT_ZMMREG,7,64
+
diff --git a/compiler/x86_64/r8664ari.inc b/compiler/x86_64/r8664ari.inc
index 85b53356b6..3747762afe 100644
--- a/compiler/x86_64/r8664ari.inc
+++ b/compiler/x86_64/r8664ari.inc
@@ -125,29 +125,93 @@
 133,
 134,
 135,
-122,
-123,
-124,
-125,
-126,
-127,
-128,
-129,
 136,
 137,
-146,
-147,
-148,
-149,
-150,
-151,
 138,
 139,
+122,
 140,
 141,
 142,
 143,
 144,
 145,
+146,
+147,
+148,
+149,
+123,
+150,
+151,
+124,
+125,
+126,
+127,
+128,
+129,
+152,
+153,
+162,
+163,
+164,
+165,
+166,
+167,
+168,
+169,
+170,
+171,
+154,
+172,
+173,
+174,
+175,
+176,
+177,
+178,
+179,
+180,
+181,
+155,
+182,
+183,
+156,
+157,
+158,
+159,
+160,
+161,
 81,
+184,
+185,
+194,
+195,
+196,
+197,
+198,
+199,
+200,
+201,
+202,
+203,
+186,
+204,
+205,
+206,
+207,
+208,
+209,
+210,
+211,
+212,
+213,
+187,
+214,
+215,
+188,
+189,
+190,
+191,
+192,
+193,
 0
diff --git a/compiler/x86_64/r8664att.inc b/compiler/x86_64/r8664att.inc
index b06dc99208..12745805a1 100644
--- a/compiler/x86_64/r8664att.inc
+++ b/compiler/x86_64/r8664att.inc
@@ -135,6 +135,22 @@
 '%xmm13',
 '%xmm14',
 '%xmm15',
+'%xmm16',
+'%xmm17',
+'%xmm18',
+'%xmm19',
+'%xmm20',
+'%xmm21',
+'%xmm22',
+'%xmm23',
+'%xmm24',
+'%xmm25',
+'%xmm26',
+'%xmm27',
+'%xmm28',
+'%xmm29',
+'%xmm30',
+'%xmm31',
 '%ymm0',
 '%ymm1',
 '%ymm2',
@@ -150,4 +166,52 @@
 '%ymm12',
 '%ymm13',
 '%ymm14',
-'%ymm15'
+'%ymm15',
+'%ymm16',
+'%ymm17',
+'%ymm18',
+'%ymm19',
+'%ymm20',
+'%ymm21',
+'%ymm22',
+'%ymm23',
+'%ymm24',
+'%ymm25',
+'%ymm26',
+'%ymm27',
+'%ymm28',
+'%ymm29',
+'%ymm30',
+'%ymm31',
+'%zmm0',
+'%zmm1',
+'%zmm2',
+'%zmm3',
+'%zmm4',
+'%zmm5',
+'%zmm6',
+'%zmm7',
+'%zmm8',
+'%zmm9',
+'%zmm10',
+'%zmm11',
+'%zmm12',
+'%zmm13',
+'%zmm14',
+'%zmm15',
+'%zmm16',
+'%zmm17',
+'%zmm18',
+'%zmm19',
+'%zmm20',
+'%zmm21',
+'%zmm22',
+'%zmm23',
+'%zmm24',
+'%zmm25',
+'%zmm26',
+'%zmm27',
+'%zmm28',
+'%zmm29',
+'%zmm30',
+'%zmm31'
diff --git a/compiler/x86_64/r8664con.inc b/compiler/x86_64/r8664con.inc
index 55c3e76a5c..45a82873ff 100644
--- a/compiler/x86_64/r8664con.inc
+++ b/compiler/x86_64/r8664con.inc
@@ -135,6 +135,22 @@ NR_XMM12 = tregister($040C000c);
 NR_XMM13 = tregister($040C000d);
 NR_XMM14 = tregister($040C000e);
 NR_XMM15 = tregister($040C000f);
+NR_XMM16 = tregister($040C0010);
+NR_XMM17 = tregister($040C0011);
+NR_XMM18 = tregister($040C0012);
+NR_XMM19 = tregister($040C0013);
+NR_XMM20 = tregister($040C0014);
+NR_XMM21 = tregister($040C0015);
+NR_XMM22 = tregister($040C0016);
+NR_XMM23 = tregister($040C0017);
+NR_XMM24 = tregister($040C0018);
+NR_XMM25 = tregister($040C0019);
+NR_XMM26 = tregister($040C001A);
+NR_XMM27 = tregister($040C001B);
+NR_XMM28 = tregister($040C001C);
+NR_XMM29 = tregister($040C001D);
+NR_XMM30 = tregister($040C001E);
+NR_XMM31 = tregister($040C001F);
 NR_YMM0 = tregister($040D0000);
 NR_YMM1 = tregister($040D0001);
 NR_YMM2 = tregister($040D0002);
@@ -151,3 +167,51 @@ NR_YMM12 = tregister($040D000c);
 NR_YMM13 = tregister($040D000d);
 NR_YMM14 = tregister($040D000e);
 NR_YMM15 = tregister($040D000f);
+NR_YMM16 = tregister($040D0010);
+NR_YMM17 = tregister($040D0011);
+NR_YMM18 = tregister($040D0012);
+NR_YMM19 = tregister($040D0013);
+NR_YMM20 = tregister($040D0014);
+NR_YMM21 = tregister($040D0015);
+NR_YMM22 = tregister($040D0016);
+NR_YMM23 = tregister($040D0017);
+NR_YMM24 = tregister($040D0018);
+NR_YMM25 = tregister($040D0019);
+NR_YMM26 = tregister($040D001a);
+NR_YMM27 = tregister($040D001b);
+NR_YMM28 = tregister($040D001c);
+NR_YMM29 = tregister($040D001d);
+NR_YMM30 = tregister($040D001e);
+NR_YMM31 = tregister($040D001f);
+NR_ZMM0 = tregister($040E0000);
+NR_ZMM1 = tregister($040E0001);
+NR_ZMM2 = tregister($040E0002);
+NR_ZMM3 = tregister($040E0003);
+NR_ZMM4 = tregister($040E0004);
+NR_ZMM5 = tregister($040E0005);
+NR_ZMM6 = tregister($040E0006);
+NR_ZMM7 = tregister($040E0007);
+NR_ZMM8 = tregister($040E0008);
+NR_ZMM9 = tregister($040E0009);
+NR_ZMM10 = tregister($040E000A);
+NR_ZMM11 = tregister($040E000B);
+NR_ZMM12 = tregister($040E000C);
+NR_ZMM13 = tregister($040E000D);
+NR_ZMM14 = tregister($040E000E);
+NR_ZMM15 = tregister($040E000F);
+NR_ZMM16 = tregister($040E0010);
+NR_ZMM17 = tregister($040E0011);
+NR_ZMM18 = tregister($040E0012);
+NR_ZMM19 = tregister($040E0013);
+NR_ZMM20 = tregister($040E0014);
+NR_ZMM21 = tregister($040E0015);
+NR_ZMM22 = tregister($040E0016);
+NR_ZMM23 = tregister($040E0017);
+NR_ZMM24 = tregister($040E0018);
+NR_ZMM25 = tregister($040E0019);
+NR_ZMM26 = tregister($040E001A);
+NR_ZMM27 = tregister($040E001B);
+NR_ZMM28 = tregister($040E001C);
+NR_ZMM29 = tregister($040E001D);
+NR_ZMM30 = tregister($040E001E);
+NR_ZMM31 = tregister($040E001F);
diff --git a/compiler/x86_64/r8664dwrf.inc b/compiler/x86_64/r8664dwrf.inc
index 6687449748..33105e4d54 100644
--- a/compiler/x86_64/r8664dwrf.inc
+++ b/compiler/x86_64/r8664dwrf.inc
@@ -135,6 +135,22 @@
 30,
 31,
 32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48,
 17,
 18,
 19,
@@ -150,4 +166,52 @@
 29,
 30,
 31,
-32
+32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48,
+17,
+18,
+19,
+20,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
+28,
+29,
+30,
+31,
+32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48
diff --git a/compiler/x86_64/r8664int.inc b/compiler/x86_64/r8664int.inc
index 94ef60f4db..9fde03ec7f 100644
--- a/compiler/x86_64/r8664int.inc
+++ b/compiler/x86_64/r8664int.inc
@@ -135,6 +135,22 @@
 'xmm13',
 'xmm14',
 'xmm15',
+'xmm16',
+'xmm17',
+'xmm18',
+'xmm19',
+'xmm20',
+'xmm21',
+'xmm22',
+'xmm23',
+'xmm24',
+'xmm25',
+'xmm26',
+'xmm27',
+'xmm28',
+'xmm29',
+'xmm30',
+'xmm31',
 'ymm0',
 'ymm1',
 'ymm2',
@@ -150,4 +166,52 @@
 'ymm12',
 'ymm13',
 'ymm14',
-'ymm15'
+'ymm15',
+'ymm16',
+'ymm17',
+'ymm18',
+'ymm19',
+'ymm20',
+'ymm21',
+'ymm22',
+'ymm23',
+'ymm24',
+'ymm25',
+'ymm26',
+'ymm27',
+'ymm28',
+'ymm29',
+'ymm30',
+'ymm31',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7',
+'zmm8',
+'zmm9',
+'zmm10',
+'zmm11',
+'zmm12',
+'zmm13',
+'zmm14',
+'zmm15',
+'zmm16',
+'zmm17',
+'zmm18',
+'zmm19',
+'zmm20',
+'zmm21',
+'zmm22',
+'zmm23',
+'zmm24',
+'zmm25',
+'zmm26',
+'zmm27',
+'zmm28',
+'zmm29',
+'zmm30',
+'zmm31'
diff --git a/compiler/x86_64/r8664iri.inc b/compiler/x86_64/r8664iri.inc
index aa7503d5cd..84ed99d14a 100644
--- a/compiler/x86_64/r8664iri.inc
+++ b/compiler/x86_64/r8664iri.inc
@@ -126,28 +126,92 @@
 133,
 134,
 135,
-122,
-123,
-124,
-125,
-126,
-127,
-128,
-129,
 136,
 137,
-146,
-147,
-148,
-149,
-150,
-151,
 138,
 139,
+122,
 140,
 141,
 142,
 143,
 144,
 145,
-81
+146,
+147,
+148,
+149,
+123,
+150,
+151,
+124,
+125,
+126,
+127,
+128,
+129,
+152,
+153,
+162,
+163,
+164,
+165,
+166,
+167,
+168,
+169,
+170,
+171,
+154,
+172,
+173,
+174,
+175,
+176,
+177,
+178,
+179,
+180,
+181,
+155,
+182,
+183,
+156,
+157,
+158,
+159,
+160,
+161,
+81,
+184,
+185,
+194,
+195,
+196,
+197,
+198,
+199,
+200,
+201,
+202,
+203,
+186,
+204,
+205,
+206,
+207,
+208,
+209,
+210,
+211,
+212,
+213,
+187,
+214,
+215,
+188,
+189,
+190,
+191,
+192,
+193
diff --git a/compiler/x86_64/r8664nasm.inc b/compiler/x86_64/r8664nasm.inc
index dffd83b9f5..5318b691e5 100644
--- a/compiler/x86_64/r8664nasm.inc
+++ b/compiler/x86_64/r8664nasm.inc
@@ -135,6 +135,22 @@
 'xmm13',
 'xmm14',
 'xmm15',
+'xmm16',
+'xmm17',
+'xmm18',
+'xmm19',
+'xmm20',
+'xmm21',
+'xmm22',
+'xmm23',
+'xmm24',
+'xmm25',
+'xmm26',
+'xmm27',
+'xmm28',
+'xmm29',
+'xmm30',
+'xmm31',
 'ymm0',
 'ymm1',
 'ymm2',
@@ -150,4 +166,52 @@
 'ymm12',
 'ymm13',
 'ymm14',
-'ymm15'
+'ymm15',
+'ymm16',
+'ymm17',
+'ymm18',
+'ymm19',
+'ymm20',
+'ymm21',
+'ymm22',
+'ymm23',
+'ymm24',
+'ymm25',
+'ymm26',
+'ymm27',
+'ymm28',
+'ymm29',
+'ymm30',
+'ymm31',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7',
+'zmm8',
+'zmm9',
+'zmm10',
+'zmm11',
+'zmm12',
+'zmm13',
+'zmm14',
+'zmm15',
+'zmm16',
+'zmm17',
+'zmm18',
+'zmm19',
+'zmm20',
+'zmm21',
+'zmm22',
+'zmm23',
+'zmm24',
+'zmm25',
+'zmm26',
+'zmm27',
+'zmm28',
+'zmm29',
+'zmm30',
+'zmm31'
diff --git a/compiler/x86_64/r8664nor.inc b/compiler/x86_64/r8664nor.inc
index fce6a32861..7c701060c0 100644
--- a/compiler/x86_64/r8664nor.inc
+++ b/compiler/x86_64/r8664nor.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86reg.dat }
-152
+216
diff --git a/compiler/x86_64/r8664num.inc b/compiler/x86_64/r8664num.inc
index e389770371..a0c5fc331c 100644
--- a/compiler/x86_64/r8664num.inc
+++ b/compiler/x86_64/r8664num.inc
@@ -135,6 +135,22 @@ tregister($040C000c),
 tregister($040C000d),
 tregister($040C000e),
 tregister($040C000f),
+tregister($040C0010),
+tregister($040C0011),
+tregister($040C0012),
+tregister($040C0013),
+tregister($040C0014),
+tregister($040C0015),
+tregister($040C0016),
+tregister($040C0017),
+tregister($040C0018),
+tregister($040C0019),
+tregister($040C001A),
+tregister($040C001B),
+tregister($040C001C),
+tregister($040C001D),
+tregister($040C001E),
+tregister($040C001F),
 tregister($040D0000),
 tregister($040D0001),
 tregister($040D0002),
@@ -150,4 +166,52 @@ tregister($040D000b),
 tregister($040D000c),
 tregister($040D000d),
 tregister($040D000e),
-tregister($040D000f)
+tregister($040D000f),
+tregister($040D0010),
+tregister($040D0011),
+tregister($040D0012),
+tregister($040D0013),
+tregister($040D0014),
+tregister($040D0015),
+tregister($040D0016),
+tregister($040D0017),
+tregister($040D0018),
+tregister($040D0019),
+tregister($040D001a),
+tregister($040D001b),
+tregister($040D001c),
+tregister($040D001d),
+tregister($040D001e),
+tregister($040D001f),
+tregister($040E0000),
+tregister($040E0001),
+tregister($040E0002),
+tregister($040E0003),
+tregister($040E0004),
+tregister($040E0005),
+tregister($040E0006),
+tregister($040E0007),
+tregister($040E0008),
+tregister($040E0009),
+tregister($040E000A),
+tregister($040E000B),
+tregister($040E000C),
+tregister($040E000D),
+tregister($040E000E),
+tregister($040E000F),
+tregister($040E0010),
+tregister($040E0011),
+tregister($040E0012),
+tregister($040E0013),
+tregister($040E0014),
+tregister($040E0015),
+tregister($040E0016),
+tregister($040E0017),
+tregister($040E0018),
+tregister($040E0019),
+tregister($040E001A),
+tregister($040E001B),
+tregister($040E001C),
+tregister($040E001D),
+tregister($040E001E),
+tregister($040E001F)
diff --git a/compiler/x86_64/r8664ot.inc b/compiler/x86_64/r8664ot.inc
index 86cea26bae..81d8f6a8ab 100644
--- a/compiler/x86_64/r8664ot.inc
+++ b/compiler/x86_64/r8664ot.inc
@@ -135,6 +135,22 @@ OT_XMMREG,
 OT_XMMREG,
 OT_XMMREG,
 OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
+OT_XMMREG,
 OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
@@ -150,4 +166,52 @@ OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
 OT_YMMREG,
-OT_YMMREG
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_YMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG,
+OT_ZMMREG
diff --git a/compiler/x86_64/r8664rni.inc b/compiler/x86_64/r8664rni.inc
index d826b3e194..cc62eed58f 100644
--- a/compiler/x86_64/r8664rni.inc
+++ b/compiler/x86_64/r8664rni.inc
@@ -117,6 +117,70 @@
 149,
 150,
 151,
+152,
+153,
+154,
+155,
+156,
+157,
+158,
+159,
+160,
+161,
+162,
+163,
+164,
+165,
+166,
+167,
+168,
+169,
+170,
+171,
+172,
+173,
+174,
+175,
+176,
+177,
+178,
+179,
+180,
+181,
+182,
+183,
+184,
+185,
+186,
+187,
+188,
+189,
+190,
+191,
+192,
+193,
+194,
+195,
+196,
+197,
+198,
+199,
+200,
+201,
+202,
+203,
+204,
+205,
+206,
+207,
+208,
+209,
+210,
+211,
+212,
+213,
+214,
+215,
 69,
 70,
 71,
diff --git a/compiler/x86_64/r8664sri.inc b/compiler/x86_64/r8664sri.inc
index aa7503d5cd..84ed99d14a 100644
--- a/compiler/x86_64/r8664sri.inc
+++ b/compiler/x86_64/r8664sri.inc
@@ -126,28 +126,92 @@
 133,
 134,
 135,
-122,
-123,
-124,
-125,
-126,
-127,
-128,
-129,
 136,
 137,
-146,
-147,
-148,
-149,
-150,
-151,
 138,
 139,
+122,
 140,
 141,
 142,
 143,
 144,
 145,
-81
+146,
+147,
+148,
+149,
+123,
+150,
+151,
+124,
+125,
+126,
+127,
+128,
+129,
+152,
+153,
+162,
+163,
+164,
+165,
+166,
+167,
+168,
+169,
+170,
+171,
+154,
+172,
+173,
+174,
+175,
+176,
+177,
+178,
+179,
+180,
+181,
+155,
+182,
+183,
+156,
+157,
+158,
+159,
+160,
+161,
+81,
+184,
+185,
+194,
+195,
+196,
+197,
+198,
+199,
+200,
+201,
+202,
+203,
+186,
+204,
+205,
+206,
+207,
+208,
+209,
+210,
+211,
+212,
+213,
+187,
+214,
+215,
+188,
+189,
+190,
+191,
+192,
+193
diff --git a/compiler/x86_64/r8664stab.inc b/compiler/x86_64/r8664stab.inc
index 6687449748..33105e4d54 100644
--- a/compiler/x86_64/r8664stab.inc
+++ b/compiler/x86_64/r8664stab.inc
@@ -135,6 +135,22 @@
 30,
 31,
 32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48,
 17,
 18,
 19,
@@ -150,4 +166,52 @@
 29,
 30,
 31,
-32
+32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48,
+17,
+18,
+19,
+20,
+21,
+22,
+23,
+24,
+25,
+26,
+27,
+28,
+29,
+30,
+31,
+32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48
diff --git a/compiler/x86_64/r8664std.inc b/compiler/x86_64/r8664std.inc
index 94ef60f4db..9fde03ec7f 100644
--- a/compiler/x86_64/r8664std.inc
+++ b/compiler/x86_64/r8664std.inc
@@ -135,6 +135,22 @@
 'xmm13',
 'xmm14',
 'xmm15',
+'xmm16',
+'xmm17',
+'xmm18',
+'xmm19',
+'xmm20',
+'xmm21',
+'xmm22',
+'xmm23',
+'xmm24',
+'xmm25',
+'xmm26',
+'xmm27',
+'xmm28',
+'xmm29',
+'xmm30',
+'xmm31',
 'ymm0',
 'ymm1',
 'ymm2',
@@ -150,4 +166,52 @@
 'ymm12',
 'ymm13',
 'ymm14',
-'ymm15'
+'ymm15',
+'ymm16',
+'ymm17',
+'ymm18',
+'ymm19',
+'ymm20',
+'ymm21',
+'ymm22',
+'ymm23',
+'ymm24',
+'ymm25',
+'ymm26',
+'ymm27',
+'ymm28',
+'ymm29',
+'ymm30',
+'ymm31',
+'zmm0',
+'zmm1',
+'zmm2',
+'zmm3',
+'zmm4',
+'zmm5',
+'zmm6',
+'zmm7',
+'zmm8',
+'zmm9',
+'zmm10',
+'zmm11',
+'zmm12',
+'zmm13',
+'zmm14',
+'zmm15',
+'zmm16',
+'zmm17',
+'zmm18',
+'zmm19',
+'zmm20',
+'zmm21',
+'zmm22',
+'zmm23',
+'zmm24',
+'zmm25',
+'zmm26',
+'zmm27',
+'zmm28',
+'zmm29',
+'zmm30',
+'zmm31'
diff --git a/compiler/x86_64/x8664nop.inc b/compiler/x86_64/x8664nop.inc
index 7cd4db7b89..3c7dd73314 100644
--- a/compiler/x86_64/x8664nop.inc
+++ b/compiler/x86_64/x8664nop.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from x86ins.dat }
-2170;
+2171;
diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc
index ceeaa126de..0e2f53f10d 100644
--- a/compiler/x86_64/x8664tab.inc
+++ b/compiler/x86_64/x8664tab.inc
@@ -11687,14 +11687,21 @@
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_xmmreg,ot_xmmreg,ot_xmmrm,ot_none);
-    code    : #241#242#248#1#236#61#80;
+    code    : #232#241#242#248#1#236#61#80;
     flags   : [if_avx,if_sandybridge]
   ),
   (
     opcode  : A_VPADDSB;
     ops     : 3;
     optypes : (ot_ymmreg,ot_ymmreg,ot_ymmrm,ot_none);
-    code    : #241#242#244#248#1#236#61#80;
+    code    : #232#241#242#244#248#1#236#61#80;
+    flags   : [if_avx2]
+  ),
+  (
+    opcode  : A_VPADDSB;
+    ops     : 3;
+    optypes : (ot_zmmreg,ot_zmmreg,ot_zmmrm,ot_none);
+    code    : #232#233#241#248#1#236#61#80;
     flags   : [if_avx2]
   ),
   (