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+ completed arm architectures

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* ldrd/strd and pld collected under the edsp define

git-svn-id: trunk@22104 -
This commit is contained in:
florian 2012-08-17 10:37:27 +00:00
parent 7588896775
commit 354cac2bb6
3 changed files with 38 additions and 17 deletions
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4
compiler/arm/aoptcpu.pas
View File

@ -370,7 +370,7 @@ Implementation
into into
strd reg1,ref strd reg1,ref
} }
else if (CPUARM_HAS_LDRDSTRD in cpu_capabilities[current_settings.cputype]) and else if (CPUARM_HAS_EDSP in cpu_capabilities[current_settings.cputype]) and
(taicpu(p).oppostfix=PF_None) and (taicpu(p).oppostfix=PF_None) and
(taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
GetNextInstruction(p,hp1) and GetNextInstruction(p,hp1) and
@ -433,7 +433,7 @@ Implementation
... ...
ldrd reg1,ref ldrd reg1,ref
} }
else if (CPUARM_HAS_LDRDSTRD in cpu_capabilities[current_settings.cputype]) and else if (CPUARM_HAS_EDSP in cpu_capabilities[current_settings.cputype]) and
{ ldrd does not allow any postfixes ... } { ldrd does not allow any postfixes ... }
(taicpu(p).oppostfix=PF_None) and (taicpu(p).oppostfix=PF_None) and
not(odd(getsupreg(taicpu(p).oper[0]^.reg))) and not(odd(getsupreg(taicpu(p).oper[0]^.reg))) and

49
compiler/arm/cpuinfo.pas
View File

@ -38,9 +38,16 @@ Type
cpu_armv5, cpu_armv5,
cpu_armv5t, cpu_armv5t,
cpu_armv5te, cpu_armv5te,
cpu_armv5tej,
cpu_armv6, cpu_armv6,
cpu_armv6k,
cpu_armv6t2,
cpu_armv6z,
cpu_armv7, cpu_armv7,
cpu_armv7m cpu_armv7a,
cpu_armv7r,
cpu_armv7m,
cpu_armv7em
); );
Const Const
@ -200,9 +207,16 @@ Const
'ARMV5', 'ARMV5',
'ARMV5T', 'ARMV5T',
'ARMV5TE', 'ARMV5TE',
'ARMV5TEJ',
'ARMV6', 'ARMV6',
'ARMV6K',
'ARMV6T2',
'ARMV6Z',
'ARMV7', 'ARMV7',
'ARMV7M' 'ARMV7A',
'ARMV7R',
'ARMV7M',
'ARMV7EM'
); );
fputypestr : array[tfputype] of string[9] = ('', fputypestr : array[tfputype] of string[9] = ('',
@ -1095,8 +1109,7 @@ Const
tcpuflags = tcpuflags =
(CPUARM_HAS_BX, (CPUARM_HAS_BX,
CPUARM_HAS_BLX, CPUARM_HAS_BLX,
CPUARM_HAS_LDRDSTRD, CPUARM_HAS_EDSP,
CPUARM_HAS_PLD,
CPUARM_HAS_REV, CPUARM_HAS_REV,
CPUARM_HAS_LDREX, CPUARM_HAS_LDREX,
CPUARM_HAS_IDIV CPUARM_HAS_IDIV
@ -1104,16 +1117,24 @@ Const
const const
cpu_capabilities : array[tcputype] of set of tcpuflags = cpu_capabilities : array[tcputype] of set of tcpuflags =
( { cpu_none } [], ( { cpu_none } [],
{ cpu_armv3 } [], { cpu_armv3 } [],
{ cpu_armv4 } [], { cpu_armv4 } [],
{ cpu_armv4t } [CPUARM_HAS_BX], { cpu_armv4t } [CPUARM_HAS_BX],
{ cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX], { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
{ cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX], { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
{ cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD], { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP],
{ cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX], { cpu_armv5tej } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP],
{ cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX], { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV] { cpu_armv6k } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ the identifier armv7 is should not be used, it is considered being equal to armv7a }
{ cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
{ cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
); );
Implementation Implementation

2
compiler/arm/narminl.pas
View File

@ -320,7 +320,7 @@ implementation
ref : treference; ref : treference;
r : tregister; r : tregister;
begin begin
if CPUARM_HAS_PLD in cpu_capabilities[current_settings.cputype] then if CPUARM_HAS_EDSP in cpu_capabilities[current_settings.cputype] then
begin begin
secondpass(left); secondpass(left);
case left.location.loc of case left.location.loc of